Yield-driven iterative robust circuit optimization algorithm
This paper proposes an equation-based multi-scenario iterative robust optimization methodology for analog/mixed-signal circuits. We show that due to local circuit performance monotonicity in random variations constraint maximization can be used to efficiently find critical constraints and worst-...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers
2010
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| Subjects: | |
| Online Access: | http://hdl.handle.net/1721.1/58966 |
| _version_ | 1826211527341899776 |
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| author | Li, Yan Stojanovic, Vladimir Marko |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Li, Yan Stojanovic, Vladimir Marko |
| author_sort | Li, Yan |
| collection | MIT |
| description | This paper proposes an equation-based multi-scenario iterative robust
optimization methodology for analog/mixed-signal circuits.
We show that due to local circuit performance monotonicity in random
variations constraint maximization can be used to efficiently
find critical constraints and worst-case scenarios of random process
variations and populate them into a multi-scenario optimization.
This algorithm scales gracefully with circuit size and is tested on
both two-stage and fully differential folded-cascode operational amplifiers
with a 90 nm predictive model. The improving yield-trends
are confirmed across process and random variations with Hspice
Monte-Carlo simulations. |
| first_indexed | 2024-09-23T15:07:24Z |
| format | Article |
| id | mit-1721.1/58966 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T15:07:24Z |
| publishDate | 2010 |
| publisher | Institute of Electrical and Electronics Engineers |
| record_format | dspace |
| spelling | mit-1721.1/589662022-09-29T12:50:31Z Yield-driven iterative robust circuit optimization algorithm Li, Yan Stojanovic, Vladimir Marko Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Stojanovic, Vladimir Marko Li, Yan Stojanovic, Vladimir Marko Algorithms Robust Circuit Optimization Variability Yield Analog Circuits This paper proposes an equation-based multi-scenario iterative robust optimization methodology for analog/mixed-signal circuits. We show that due to local circuit performance monotonicity in random variations constraint maximization can be used to efficiently find critical constraints and worst-case scenarios of random process variations and populate them into a multi-scenario optimization. This algorithm scales gracefully with circuit size and is tested on both two-stage and fully differential folded-cascode operational amplifiers with a 90 nm predictive model. The improving yield-trends are confirmed across process and random variations with Hspice Monte-Carlo simulations. Massachusetts Institute of Technology. Center for Integrated Circuits and Systems 2010-10-08T14:59:41Z 2010-10-08T14:59:41Z 2009-08 2009-07 Article http://purl.org/eprint/type/JournalArticle 978-1-6055-8497-3 0738-100X INSPEC Accession Number: 10844460 http://hdl.handle.net/1721.1/58966 Yan Li; Stojanovic, V.; , "Yield-driven iterative robust circuit optimization algorithm," Design Automation Conference, 2009. DAC '09. 46th ACM/IEEE , vol., no., pp.599-604, 26-31 July 2009. Copyright 2009 ACM en_US http://doi.acm.org/10.1145/1629911.1630065 Proceedings of the 46th ACM/IEEE Design Automation Conference, 2009 Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. application/pdf Institute of Electrical and Electronics Engineers IEEE |
| spellingShingle | Algorithms Robust Circuit Optimization Variability Yield Analog Circuits Li, Yan Stojanovic, Vladimir Marko Yield-driven iterative robust circuit optimization algorithm |
| title | Yield-driven iterative robust circuit optimization algorithm |
| title_full | Yield-driven iterative robust circuit optimization algorithm |
| title_fullStr | Yield-driven iterative robust circuit optimization algorithm |
| title_full_unstemmed | Yield-driven iterative robust circuit optimization algorithm |
| title_short | Yield-driven iterative robust circuit optimization algorithm |
| title_sort | yield driven iterative robust circuit optimization algorithm |
| topic | Algorithms Robust Circuit Optimization Variability Yield Analog Circuits |
| url | http://hdl.handle.net/1721.1/58966 |
| work_keys_str_mv | AT liyan yielddriveniterativerobustcircuitoptimizationalgorithm AT stojanovicvladimirmarko yielddriveniterativerobustcircuitoptimizationalgorithm |