Design and performance evaluation of a low-power data-line SRAM sense amplifier
The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. The heavy bit-and data-line capacitances are the major road blocks to its performance. A high-performance SRAM is proposed using a 1.8 V/0.18 à ¿m CMOS standard process from Chartered Semiconductor Manufac...
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| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers
2010
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| Online Access: | http://hdl.handle.net/1721.1/59362 |
| _version_ | 1826212603237498880 |
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| author | Fu, Haitao Yeo, Kiat-Seng Do, Anh-Tuan Kong, Zhi-Hui |
| author2 | Massachusetts Institute of Technology. Department of Materials Science and Engineering |
| author_facet | Massachusetts Institute of Technology. Department of Materials Science and Engineering Fu, Haitao Yeo, Kiat-Seng Do, Anh-Tuan Kong, Zhi-Hui |
| author_sort | Fu, Haitao |
| collection | MIT |
| description | The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. The heavy bit-and data-line capacitances are the major road blocks to its performance. A high-performance SRAM is proposed using a 1.8 V/0.18 à ¿m CMOS standard process from Chartered Semiconductor Manufacturing Ltd (CHRT). It incorporates a discharging mechanism that helps eliminating the waiting time during the read operation, hence offering a faster sensing speed and lower power consumption. Our post-layout simulation results have shown that it improves the sensing speed and power consumption by 51.4%, and 62.47%, respectively when compared with the best published design. The total power-delay-product (PDP) is 81.79% better. Furthermore, it can operate at a supply voltage as low as 0.8 V with a high stability to the bit-line capacitances variation and mismatch. |
| first_indexed | 2024-09-23T15:29:11Z |
| format | Article |
| id | mit-1721.1/59362 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T15:29:11Z |
| publishDate | 2010 |
| publisher | Institute of Electrical and Electronics Engineers |
| record_format | dspace |
| spelling | mit-1721.1/593622022-10-02T02:45:52Z Design and performance evaluation of a low-power data-line SRAM sense amplifier Fu, Haitao Yeo, Kiat-Seng Do, Anh-Tuan Kong, Zhi-Hui Massachusetts Institute of Technology. Department of Materials Science and Engineering Fu, Haitao Fu, Haitao CMOS integrated circuits SRAM chips amplifiers cache storage logic design low-power electronics system-on-chip CHRT CMOS standard process Chartered Semiconductor Manufacturing Ltd. bit-line capacitances variation data-line capacitances discharging mechanism electronic industry low-power data-line SRAM sense amplifier evaluation lower power consumption post-layout simulation size 0.18 mum total power-delay-product voltage 1.8 V The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. The heavy bit-and data-line capacitances are the major road blocks to its performance. A high-performance SRAM is proposed using a 1.8 V/0.18 à ¿m CMOS standard process from Chartered Semiconductor Manufacturing Ltd (CHRT). It incorporates a discharging mechanism that helps eliminating the waiting time during the read operation, hence offering a faster sensing speed and lower power consumption. Our post-layout simulation results have shown that it improves the sensing speed and power consumption by 51.4%, and 62.47%, respectively when compared with the best published design. The total power-delay-product (PDP) is 81.79% better. Furthermore, it can operate at a supply voltage as low as 0.8 V with a high stability to the bit-line capacitances variation and mismatch. 2010-10-15T14:43:49Z 2010-10-15T14:43:49Z 2010-02 2009-12 Article http://purl.org/eprint/type/JournalArticle 978-9-8108-2468-6 INSPEC Accession Number: 11105427 http://hdl.handle.net/1721.1/59362 Fu, Haitao, Kiat-Seng Yeo, Anh-Tuan Do, and Zhi-Hui Kong (2010). "Design and performance evaluation of a low-power data-line SRAM sense amplifier." Proceedings of the 2009 12th International Symposium on Integrated Circuits, ISIC'09 (Piscataway, N.J.: IEEE): 291-294. © 2010 IEEE en_US http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5403784 Proceedings of the 2009 12th International Symposium on Integrated Circuits, ISIC '09 Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. application/pdf Institute of Electrical and Electronics Engineers IEEE |
| spellingShingle | CMOS integrated circuits SRAM chips amplifiers cache storage logic design low-power electronics system-on-chip CHRT CMOS standard process Chartered Semiconductor Manufacturing Ltd. bit-line capacitances variation data-line capacitances discharging mechanism electronic industry low-power data-line SRAM sense amplifier evaluation lower power consumption post-layout simulation size 0.18 mum total power-delay-product voltage 1.8 V Fu, Haitao Yeo, Kiat-Seng Do, Anh-Tuan Kong, Zhi-Hui Design and performance evaluation of a low-power data-line SRAM sense amplifier |
| title | Design and performance evaluation of a low-power data-line SRAM sense amplifier |
| title_full | Design and performance evaluation of a low-power data-line SRAM sense amplifier |
| title_fullStr | Design and performance evaluation of a low-power data-line SRAM sense amplifier |
| title_full_unstemmed | Design and performance evaluation of a low-power data-line SRAM sense amplifier |
| title_short | Design and performance evaluation of a low-power data-line SRAM sense amplifier |
| title_sort | design and performance evaluation of a low power data line sram sense amplifier |
| topic | CMOS integrated circuits SRAM chips amplifiers cache storage logic design low-power electronics system-on-chip CHRT CMOS standard process Chartered Semiconductor Manufacturing Ltd. bit-line capacitances variation data-line capacitances discharging mechanism electronic industry low-power data-line SRAM sense amplifier evaluation lower power consumption post-layout simulation size 0.18 mum total power-delay-product voltage 1.8 V |
| url | http://hdl.handle.net/1721.1/59362 |
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