Design and performance evaluation of a low-power data-line SRAM sense amplifier

Design and performance evaluation of a low-power data-line SRAM sense amplifier

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The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. The heavy bit-and data-line capacitances are the major road blocks to its performance. A high-performance SRAM is proposed using a 1.8 V/0.18 à ¿m CMOS standard process from Chartered Semiconductor Manufac...

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Bibliographic Details
Main Authors: Fu, Haitao, Yeo, Kiat-Seng, Do, Anh-Tuan, Kong, Zhi-Hui
Other Authors: Massachusetts Institute of Technology. Department of Materials Science and Engineering
Format: Article
Language:en_US
Published: Institute of Electrical and Electronics Engineers 2010
Subjects:
CMOS integrated circuits
SRAM chips
amplifiers
cache storage
logic design
low-power electronics
system-on-chip
CHRT
CMOS standard process
Chartered Semiconductor Manufacturing Ltd.
bit-line capacitances variation
data-line capacitances
discharging mechanism
electronic industry
low-power data-line SRAM sense amplifier evaluation
lower power consumption
post-layout simulation
size 0.18 mum
total power-delay-product
voltage 1.8 V
Online Access:http://hdl.handle.net/1721.1/59362

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