Designing Energy-Efficient Low-Diameter On-chip Networks with Equalized Interconnects
In a power and area constrained multicore system, the on-chip communication network needs to be carefully designed to maximize the system performance and programmer productivity while minimizing energy and area. In this paper, we explore the design of energy-efficient low-diameter networks (flattene...
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| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers
2010
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| Online Access: | http://hdl.handle.net/1721.1/59419 |
| _version_ | 1811070777699598336 |
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| author | Joshi, Ajay J. Kim, Byungsub Stojanovic, Vladimir Marko |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Joshi, Ajay J. Kim, Byungsub Stojanovic, Vladimir Marko |
| author_sort | Joshi, Ajay J. |
| collection | MIT |
| description | In a power and area constrained multicore system, the on-chip communication network needs to be carefully designed to maximize the system performance and programmer productivity while minimizing energy and area. In this paper, we explore the design of energy-efficient low-diameter networks (flattened butterfly and Clos) using equalized on-chip interconnects. These low-diameter networks are attractive as they can potentially provide uniformly high throughput and low latency across various traffic patterns, but require efficient global communication channels. In our case study, for a 64-tile system, the use of equalization for the wire channels in low-diameter networks provides 2x reduction in power with no loss in system performance compared to repeater-inserted wire channels. The use of virtual channels in routers further reduces the power of the network by 25-50% and wire area by 2x. |
| first_indexed | 2024-09-23T08:41:24Z |
| format | Article |
| id | mit-1721.1/59419 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T08:41:24Z |
| publishDate | 2010 |
| publisher | Institute of Electrical and Electronics Engineers |
| record_format | dspace |
| spelling | mit-1721.1/594192022-09-23T13:53:20Z Designing Energy-Efficient Low-Diameter On-chip Networks with Equalized Interconnects Joshi, Ajay J. Kim, Byungsub Stojanovic, Vladimir Marko Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Stojanovic, Vladimir Marko Joshi, Ajay J. Kim, Byungsub Stojanovic, Vladimir Marko on-chip network multicore system low power equalized interconnects In a power and area constrained multicore system, the on-chip communication network needs to be carefully designed to maximize the system performance and programmer productivity while minimizing energy and area. In this paper, we explore the design of energy-efficient low-diameter networks (flattened butterfly and Clos) using equalized on-chip interconnects. These low-diameter networks are attractive as they can potentially provide uniformly high throughput and low latency across various traffic patterns, but require efficient global communication channels. In our case study, for a 64-tile system, the use of equalization for the wire channels in low-diameter networks provides 2x reduction in power with no loss in system performance compared to repeater-inserted wire channels. The use of virtual channels in routers further reduces the power of the network by 25-50% and wire area by 2x. Intel Corporation 2010-10-20T12:44:48Z 2010-10-20T12:44:48Z 2009-09 2009-08 Article http://purl.org/eprint/type/ConferencePaper 978-0-7695-3847-1 1550-4794 INSPEC Accession Number: 10869173 http://hdl.handle.net/1721.1/59419 Joshi, A., B. Kim, and V. Stojanovic. “Designing Energy-Efficient Low-Diameter On-Chip Networks with Equalized Interconnects.” High Performance Interconnects, 2009. HOTI 2009. 17th IEEE Symposium on. 2009. 3-12. © Copyright 2010 IEEE en_US http://dx.doi.org/10.1109/HOTI.2009.13 17th IEEE Symposium on High Performance Interconnects, 2009. HOTI 2009. Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. application/pdf Institute of Electrical and Electronics Engineers IEEE |
| spellingShingle | on-chip network multicore system low power equalized interconnects Joshi, Ajay J. Kim, Byungsub Stojanovic, Vladimir Marko Designing Energy-Efficient Low-Diameter On-chip Networks with Equalized Interconnects |
| title | Designing Energy-Efficient Low-Diameter On-chip Networks with Equalized Interconnects |
| title_full | Designing Energy-Efficient Low-Diameter On-chip Networks with Equalized Interconnects |
| title_fullStr | Designing Energy-Efficient Low-Diameter On-chip Networks with Equalized Interconnects |
| title_full_unstemmed | Designing Energy-Efficient Low-Diameter On-chip Networks with Equalized Interconnects |
| title_short | Designing Energy-Efficient Low-Diameter On-chip Networks with Equalized Interconnects |
| title_sort | designing energy efficient low diameter on chip networks with equalized interconnects |
| topic | on-chip network multicore system low power equalized interconnects |
| url | http://hdl.handle.net/1721.1/59419 |
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