Darsim: A Parallel Cycle-Level NoC Simulator
We present DARSIM, a parallel, highly configurable, cycle-level network-on-chip simulator based on an ingress-queued wormhole router architecture. The parallel simulation engine offers cycle-accurate as well as periodic synchronization, permitting tradeoffs between perfect accuracy and high speed wi...
| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | en_US |
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2010
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| Online Access: | http://hdl.handle.net/1721.1/59832 https://orcid.org/0000-0001-8253-7714 https://orcid.org/0000-0001-5490-2323 |
| _version_ | 1826197523201523712 |
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| author | Lis, Mieszko Shim, Keun Sup Cho, Myong Hyon Ren, Pengju Khan, Omer Devadas, Srinivas |
| author2 | Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory |
| author_facet | Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory Lis, Mieszko Shim, Keun Sup Cho, Myong Hyon Ren, Pengju Khan, Omer Devadas, Srinivas |
| author_sort | Lis, Mieszko |
| collection | MIT |
| description | We present DARSIM, a parallel, highly configurable, cycle-level network-on-chip simulator based on an ingress-queued wormhole router architecture. The parallel simulation engine offers cycle-accurate as well as periodic synchronization, permitting tradeoffs between perfect accuracy and high speed with very good accuracy. When run on four separate physical cores, speedups can exceed a factor of 3.5, while when eight threads are mapped to the same cores via hyperthreading, simulation speeds up as much as five-fold. Most hardware parameters are configurable, including geometry, bandwidth, crossbar dimensions, and pipeline depths. A highly parametrized table-based design allows a variety of routing and virtual channel allocation algorithms out of the box, ranging from simple DOR routing to complex Valiant, ROMM, or PROM schemes, BSOR, and adaptive routing. DARSIM can run in network-only mode using traces or directly emulate a MIPS-based multicore. Sources are freely available under the open-source MIT license. |
| first_indexed | 2024-09-23T10:48:57Z |
| format | Article |
| id | mit-1721.1/59832 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T10:48:57Z |
| publishDate | 2010 |
| record_format | dspace |
| spelling | mit-1721.1/598322022-09-30T23:13:52Z Darsim: A Parallel Cycle-Level NoC Simulator Lis, Mieszko Shim, Keun Sup Cho, Myong Hyon Ren, Pengju Khan, Omer Devadas, Srinivas Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Devadas, Srinivas Devadas, Srinivas Lis, Mieszko Shim, Keun Sup Cho, Myong Hyon Khan, Omer We present DARSIM, a parallel, highly configurable, cycle-level network-on-chip simulator based on an ingress-queued wormhole router architecture. The parallel simulation engine offers cycle-accurate as well as periodic synchronization, permitting tradeoffs between perfect accuracy and high speed with very good accuracy. When run on four separate physical cores, speedups can exceed a factor of 3.5, while when eight threads are mapped to the same cores via hyperthreading, simulation speeds up as much as five-fold. Most hardware parameters are configurable, including geometry, bandwidth, crossbar dimensions, and pipeline depths. A highly parametrized table-based design allows a variety of routing and virtual channel allocation algorithms out of the box, ranging from simple DOR routing to complex Valiant, ROMM, or PROM schemes, BSOR, and adaptive routing. DARSIM can run in network-only mode using traces or directly emulate a MIPS-based multicore. Sources are freely available under the open-source MIT license. 2010-11-05T17:52:41Z 2010-11-05T17:52:41Z 2010 Article http://purl.org/eprint/type/ConferencePaper http://hdl.handle.net/1721.1/59832 Lis, Mieszko et al. “DARSIM: a parallel cycle-level NoC simulator.” 2010. https://orcid.org/0000-0001-8253-7714 https://orcid.org/0000-0001-5490-2323 en_US Attribution-Noncommercial-Share Alike 3.0 Unported http://creativecommons.org/licenses/by-nc-sa/3.0/ application/pdf MIT web domain |
| spellingShingle | Lis, Mieszko Shim, Keun Sup Cho, Myong Hyon Ren, Pengju Khan, Omer Devadas, Srinivas Darsim: A Parallel Cycle-Level NoC Simulator |
| title | Darsim: A Parallel Cycle-Level NoC Simulator |
| title_full | Darsim: A Parallel Cycle-Level NoC Simulator |
| title_fullStr | Darsim: A Parallel Cycle-Level NoC Simulator |
| title_full_unstemmed | Darsim: A Parallel Cycle-Level NoC Simulator |
| title_short | Darsim: A Parallel Cycle-Level NoC Simulator |
| title_sort | darsim a parallel cycle level noc simulator |
| url | http://hdl.handle.net/1721.1/59832 https://orcid.org/0000-0001-8253-7714 https://orcid.org/0000-0001-5490-2323 |
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