A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS
The design of compact low-power I/O transceivers continues to be a challenge for both chip-to-chip and backplane applications. The introduction of dense fine-pitch silicon packaging technologies, that in principle are capable of supporting tens of thousands of high-data-rate I/O for local chip-to-ch...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers
2010
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| Online Access: | http://hdl.handle.net/1721.1/59837 |
| _version_ | 1811088103570407424 |
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| author | Kim, Byungsub Dickson, Timothy O. Liu, Yong Bulzacchelli, John F. Friedman, Daniel J. |
| author2 | Massachusetts Institute of Technology. Research Laboratory of Electronics |
| author_facet | Massachusetts Institute of Technology. Research Laboratory of Electronics Kim, Byungsub Dickson, Timothy O. Liu, Yong Bulzacchelli, John F. Friedman, Daniel J. |
| author_sort | Kim, Byungsub |
| collection | MIT |
| description | The design of compact low-power I/O transceivers continues to be a challenge for both chip-to-chip and backplane applications. The introduction of dense fine-pitch silicon packaging technologies, that in principle are capable of supporting tens of thousands of high-data-rate I/O for local chip-to-chip interconnect, will make I/O area and power requirements even more stringent.This paper describes an alternative low-power compact I/O transceiver with RX equalization that achieves the required multi-bit postcursor cancellation without a high tap-count DFE. While this work targets data transmission over Si carrier links at rates up to 10Gb/s, it is also relevant to backplane channels. |
| first_indexed | 2024-09-23T13:56:19Z |
| format | Article |
| id | mit-1721.1/59837 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T13:56:19Z |
| publishDate | 2010 |
| publisher | Institute of Electrical and Electronics Engineers |
| record_format | dspace |
| spelling | mit-1721.1/598372022-09-28T17:12:09Z A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS Kim, Byungsub Dickson, Timothy O. Liu, Yong Bulzacchelli, John F. Friedman, Daniel J. Massachusetts Institute of Technology. Research Laboratory of Electronics Kim, Byungsub Kim, Byungsub The design of compact low-power I/O transceivers continues to be a challenge for both chip-to-chip and backplane applications. The introduction of dense fine-pitch silicon packaging technologies, that in principle are capable of supporting tens of thousands of high-data-rate I/O for local chip-to-chip interconnect, will make I/O area and power requirements even more stringent.This paper describes an alternative low-power compact I/O transceiver with RX equalization that achieves the required multi-bit postcursor cancellation without a high tap-count DFE. While this work targets data transmission over Si carrier links at rates up to 10Gb/s, it is also relevant to backplane channels. 2010-11-05T18:54:39Z 2010-11-05T18:54:39Z 2009-05 2009-02 Article http://purl.org/eprint/type/JournalArticle 978-1-4244-3458-9 INSPEC Accession Number: 10727922 http://hdl.handle.net/1721.1/59837 Yong Liu et al. “A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS.” Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International. 2009. 182-183,183a. © 2009 Institute of Electrical and Electronics Engineers. en_US http://dx.doi.org/10.1109/ISSCC.2009.4977368 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009 Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. application/pdf Institute of Electrical and Electronics Engineers IEEE |
| spellingShingle | Kim, Byungsub Dickson, Timothy O. Liu, Yong Bulzacchelli, John F. Friedman, Daniel J. A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS |
| title | A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS |
| title_full | A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS |
| title_fullStr | A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS |
| title_full_unstemmed | A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS |
| title_short | A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS |
| title_sort | 10gb s compact low power serial i o with dfe iir equalization in 65nm cmos |
| url | http://hdl.handle.net/1721.1/59837 |
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