A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS

A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS

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The design of compact low-power I/O transceivers continues to be a challenge for both chip-to-chip and backplane applications. The introduction of dense fine-pitch silicon packaging technologies, that in principle are capable of supporting tens of thousands of high-data-rate I/O for local chip-to-ch...

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Bibliographic Details
Main Authors:	Kim, Byungsub, Dickson, Timothy O., Liu, Yong, Bulzacchelli, John F., Friedman, Daniel J.
Other Authors:	Massachusetts Institute of Technology. Research Laboratory of Electronics
Format:	Article
Language:	en_US
Published:	Institute of Electrical and Electronics Engineers 2010
Online Access:	http://hdl.handle.net/1721.1/59837

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