A 0.13[mu]m CMOS 78dB SNDR 87mW 20MHz BW CT [Delta Sigma] ADC with VCO-based integrator and quantizer

In this paper we demonstrate a new technique that eliminates the impact of K[subscript v] nonlinearity by preserving the integral relationship of the VCO output phase to the input signal. Leveraging the VCO output phase directly precludes the need to span the entire nonlinear K[subscript v] characte...

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Bibliographic Details
Main Author: Park, Matthew
Other Authors: Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Format: Article
Language:en_US
Published: Institute of Electrical and Electronics Engineers 2010
Online Access:http://hdl.handle.net/1721.1/60071
Description
Summary:In this paper we demonstrate a new technique that eliminates the impact of K[subscript v] nonlinearity by preserving the integral relationship of the VCO output phase to the input signal. Leveraging the VCO output phase directly precludes the need to span the entire nonlinear K[subscript v] characteristic since small perturbations (in the range of 10s of mV) at the tuning node are sufficient to shift the VCO phase by a substantial amount. Since an open-loop VCO is sensitive to frequency offsets and drift, and easily saturates its phase detector for large input signals, some form of negative feedback is necessary. Here, a multibit DAC subtracts the previously quantized phase value from the VCO input, creating a residue that is integrated during the next clock cycle. This feedback loop not only allows large signals to drive the VCO without incurring distortion from K[subscript v] nonlinearity, but also it is a 1s,-order CT DeltaSigma ADC loop, and it therefore 1s,-order shapes quantization noise.