A Multiprocessor Architecture Using Modular Arithmetic for Very High Precision Computation
We outline a multiprocessor architecture that uses modular arithmetic to implement numerical computation with 900 bits of intermediate precision. A proposed prototype, to be implemented with off-the-shelf parts, will perform high-precision arithmetic as fast as some workstations and mini- comp...
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| Language: | en_US |
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2004
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| Online Access: | http://hdl.handle.net/1721.1/6021 |
| _version_ | 1811096144625795072 |
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| author | Wu, Henry M. |
| author_facet | Wu, Henry M. |
| author_sort | Wu, Henry M. |
| collection | MIT |
| description | We outline a multiprocessor architecture that uses modular arithmetic to implement numerical computation with 900 bits of intermediate precision. A proposed prototype, to be implemented with off-the-shelf parts, will perform high-precision arithmetic as fast as some workstations and mini- computers can perform IEEE double-precision arithmetic. We discuss how the structure of modular arithmetic conveniently maps into a simple, pipelined multiprocessor architecture. We present techniques we developed to overcome a few classical drawbacks of modular arithmetic. Our architecture is suitable to and essential for the study of chaotic dynamical systems. |
| first_indexed | 2024-09-23T16:38:52Z |
| id | mit-1721.1/6021 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T16:38:52Z |
| publishDate | 2004 |
| record_format | dspace |
| spelling | mit-1721.1/60212019-04-11T00:13:19Z A Multiprocessor Architecture Using Modular Arithmetic for Very High Precision Computation Wu, Henry M. modular arithmetic computer architecture multiprocessor sresidue number system computer arithmetic pipelining chaos We outline a multiprocessor architecture that uses modular arithmetic to implement numerical computation with 900 bits of intermediate precision. A proposed prototype, to be implemented with off-the-shelf parts, will perform high-precision arithmetic as fast as some workstations and mini- computers can perform IEEE double-precision arithmetic. We discuss how the structure of modular arithmetic conveniently maps into a simple, pipelined multiprocessor architecture. We present techniques we developed to overcome a few classical drawbacks of modular arithmetic. Our architecture is suitable to and essential for the study of chaotic dynamical systems. 2004-10-04T14:36:07Z 2004-10-04T14:36:07Z 1989-04-01 AIM-1119 http://hdl.handle.net/1721.1/6021 en_US AIM-1119 12 p. 2230694 bytes 827297 bytes application/postscript application/pdf application/postscript application/pdf |
| spellingShingle | modular arithmetic computer architecture multiprocessor sresidue number system computer arithmetic pipelining chaos Wu, Henry M. A Multiprocessor Architecture Using Modular Arithmetic for Very High Precision Computation |
| title | A Multiprocessor Architecture Using Modular Arithmetic for Very High Precision Computation |
| title_full | A Multiprocessor Architecture Using Modular Arithmetic for Very High Precision Computation |
| title_fullStr | A Multiprocessor Architecture Using Modular Arithmetic for Very High Precision Computation |
| title_full_unstemmed | A Multiprocessor Architecture Using Modular Arithmetic for Very High Precision Computation |
| title_short | A Multiprocessor Architecture Using Modular Arithmetic for Very High Precision Computation |
| title_sort | multiprocessor architecture using modular arithmetic for very high precision computation |
| topic | modular arithmetic computer architecture multiprocessor sresidue number system computer arithmetic pipelining chaos |
| url | http://hdl.handle.net/1721.1/6021 |
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