A performance measure of page mode dram as a second level cache in microprocessors
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1992.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2011
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| Online Access: | http://hdl.handle.net/1721.1/60734 |
| _version_ | 1826201693241475072 |
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| author | Shoemaker, David R. (David Robert) |
| author2 | Steve Ward. |
| author_facet | Steve Ward. Shoemaker, David R. (David Robert) |
| author_sort | Shoemaker, David R. (David Robert) |
| collection | MIT |
| description | Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1992. |
| first_indexed | 2024-09-23T11:55:15Z |
| format | Thesis |
| id | mit-1721.1/60734 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T11:55:15Z |
| publishDate | 2011 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/607342019-04-12T16:10:02Z A performance measure of page mode dram as a second level cache in microprocessors Shoemaker, David R. (David Robert) Steve Ward. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science Electrical Engineering and Computer Science Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1992. Includes bibliographical references (leaf 151). by David R. Shoemaker. M.S. 2011-01-26T14:16:19Z 2011-01-26T14:16:19Z 1992 1992 Thesis http://hdl.handle.net/1721.1/60734 27001331 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 151 leaves application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science Shoemaker, David R. (David Robert) A performance measure of page mode dram as a second level cache in microprocessors |
| title | A performance measure of page mode dram as a second level cache in microprocessors |
| title_full | A performance measure of page mode dram as a second level cache in microprocessors |
| title_fullStr | A performance measure of page mode dram as a second level cache in microprocessors |
| title_full_unstemmed | A performance measure of page mode dram as a second level cache in microprocessors |
| title_short | A performance measure of page mode dram as a second level cache in microprocessors |
| title_sort | performance measure of page mode dram as a second level cache in microprocessors |
| topic | Electrical Engineering and Computer Science |
| url | http://hdl.handle.net/1721.1/60734 |
| work_keys_str_mv | AT shoemakerdavidrdavidrobert aperformancemeasureofpagemodedramasasecondlevelcacheinmicroprocessors AT shoemakerdavidrdavidrobert performancemeasureofpagemodedramasasecondlevelcacheinmicroprocessors |