Proposed Instructions on the GE 635 for List Processing and Push Down Stacks
The instructions that transmit data between the index registers and the memory work only on the left half (address) portion of memory. These instructions are LDXn (load index n from address of storage word). And STXn (store the contents of index n in address of storage word). The effective address o...
| Main Author: | |
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| Language: | en_US |
| Published: |
2004
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| Online Access: | http://hdl.handle.net/1721.1/6114 |
| _version_ | 1826211206450380800 |
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| author | Levin, Michael |
| author_facet | Levin, Michael |
| author_sort | Levin, Michael |
| collection | MIT |
| description | The instructions that transmit data between the index registers and the memory work only on the left half (address) portion of memory. These instructions are LDXn (load index n from address of storage word). And STXn (store the contents of index n in address of storage word). The effective address of both of these instructions includes modification by index registers. A corresponding set of instructions for transmitting data to or from the right half of memory would facilitate list structure operations. The present order code makes it impossible to so list-chaining operations (car or cdr) without disturbing the A or Q registers. |
| first_indexed | 2024-09-23T15:02:15Z |
| id | mit-1721.1/6114 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T15:02:15Z |
| publishDate | 2004 |
| record_format | dspace |
| spelling | mit-1721.1/61142019-04-11T02:47:41Z Proposed Instructions on the GE 635 for List Processing and Push Down Stacks Levin, Michael The instructions that transmit data between the index registers and the memory work only on the left half (address) portion of memory. These instructions are LDXn (load index n from address of storage word). And STXn (store the contents of index n in address of storage word). The effective address of both of these instructions includes modification by index registers. A corresponding set of instructions for transmitting data to or from the right half of memory would facilitate list structure operations. The present order code makes it impossible to so list-chaining operations (car or cdr) without disturbing the A or Q registers. 2004-10-04T14:39:53Z 2004-10-04T14:39:53Z 1964-09-01 AIM-072 http://hdl.handle.net/1721.1/6114 en_US AIM-072 1162914 bytes 88986 bytes application/postscript application/pdf application/postscript application/pdf |
| spellingShingle | Levin, Michael Proposed Instructions on the GE 635 for List Processing and Push Down Stacks |
| title | Proposed Instructions on the GE 635 for List Processing and Push Down Stacks |
| title_full | Proposed Instructions on the GE 635 for List Processing and Push Down Stacks |
| title_fullStr | Proposed Instructions on the GE 635 for List Processing and Push Down Stacks |
| title_full_unstemmed | Proposed Instructions on the GE 635 for List Processing and Push Down Stacks |
| title_short | Proposed Instructions on the GE 635 for List Processing and Push Down Stacks |
| title_sort | proposed instructions on the ge 635 for list processing and push down stacks |
| url | http://hdl.handle.net/1721.1/6114 |
| work_keys_str_mv | AT levinmichael proposedinstructionsonthege635forlistprocessingandpushdownstacks |