Photonic Device Layout Within the Foundry CMOS Design Environment
A design methodology to layout photonic devices within standard electronic complementary metal-oxide-semiconductor (CMOS) foundry data preparation flows is described. This platform has enabled the fabrication of designs in three foundry scaled-CMOS processes from two semiconductor manufacturers.
| Main Authors: | , |
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| Other Authors: | |
| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers
2011
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| Online Access: | http://hdl.handle.net/1721.1/61756 https://orcid.org/0000-0003-0420-2235 |
| _version_ | 1811081548208799744 |
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| author | Orcutt, Jason Scott Ram, Rajeev J. |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Orcutt, Jason Scott Ram, Rajeev J. |
| author_sort | Orcutt, Jason Scott |
| collection | MIT |
| description | A design methodology to layout photonic devices within standard electronic complementary metal-oxide-semiconductor (CMOS) foundry data preparation flows is described. This platform has enabled the fabrication of designs in three foundry scaled-CMOS processes from two semiconductor manufacturers. |
| first_indexed | 2024-09-23T11:47:58Z |
| format | Article |
| id | mit-1721.1/61756 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T11:47:58Z |
| publishDate | 2011 |
| publisher | Institute of Electrical and Electronics Engineers |
| record_format | dspace |
| spelling | mit-1721.1/617562022-10-01T06:06:51Z Photonic Device Layout Within the Foundry CMOS Design Environment Orcutt, Jason Scott Ram, Rajeev J. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology. Research Laboratory of Electronics Ram, Rajeev J. Orcutt, Jason Scott Ram, Rajeev J. A design methodology to layout photonic devices within standard electronic complementary metal-oxide-semiconductor (CMOS) foundry data preparation flows is described. This platform has enabled the fabrication of designs in three foundry scaled-CMOS processes from two semiconductor manufacturers. United States. Defense Advanced Research Projects Agency (DARPA) National Science Foundation (U.S.) 2011-03-21T21:17:21Z 2011-03-21T21:17:21Z 2010-03 2009-11 Article http://purl.org/eprint/type/JournalArticle 1041-1135 INSPEC Accession Number: 11180069 http://hdl.handle.net/1721.1/61756 Orcutt, J.S., and R.J. Ram. “Photonic Device Layout Within the Foundry CMOS Design Environment.” Photonics Technology Letters, IEEE 22.8 (2010): 544-546. © Copyright 2010 IEEE https://orcid.org/0000-0003-0420-2235 en_US http://dx.doi.org/10.1109/lpt.2010.2041445 IEEE Photonics Technology Letters Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. application/pdf Institute of Electrical and Electronics Engineers IEEE |
| spellingShingle | Orcutt, Jason Scott Ram, Rajeev J. Photonic Device Layout Within the Foundry CMOS Design Environment |
| title | Photonic Device Layout Within the Foundry CMOS Design Environment |
| title_full | Photonic Device Layout Within the Foundry CMOS Design Environment |
| title_fullStr | Photonic Device Layout Within the Foundry CMOS Design Environment |
| title_full_unstemmed | Photonic Device Layout Within the Foundry CMOS Design Environment |
| title_short | Photonic Device Layout Within the Foundry CMOS Design Environment |
| title_sort | photonic device layout within the foundry cmos design environment |
| url | http://hdl.handle.net/1721.1/61756 https://orcid.org/0000-0003-0420-2235 |
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