Physical vs. Virtual Express Topologies with Low-Swing Links for Future Many-core NoCs
The number of cores present on-chip is increasing rapidly. The on-chip network that connects these cores needs to scale efficiently. The topology of on-chip networks is an important design choice that affects how these networks scale. Most current on-chip networks use 2-D mesh topologies which do no...
| Main Authors: | , , , , |
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| Other Authors: | |
| Format: | Article |
| Language: | en_US |
| Published: |
Institute of Electrical and Electronics Engineers
2011
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| Online Access: | http://hdl.handle.net/1721.1/61948 https://orcid.org/0000-0001-9010-6519 https://orcid.org/0000-0003-1284-6620 |