A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS
An 8T SRAM fabricated in 45 nm SOI CMOS exhibits voltage scalable operation from 1.2 V down to 0.57 V with access times from 400 ps to 3.4 ns. Timing variation and the challenge of low-voltage operation are addressed with an AC-coupled sense amplifier. An area efficient data path is achieved with a...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers
2011
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| Online Access: | http://hdl.handle.net/1721.1/62194 https://orcid.org/0000-0002-5977-2748 |
| _version_ | 1811078981856788480 |
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| author | Qazi, Masood Stawiasz, Kevin Chang, Leland Chandrakasan, Anantha P. |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Qazi, Masood Stawiasz, Kevin Chang, Leland Chandrakasan, Anantha P. |
| author_sort | Qazi, Masood |
| collection | MIT |
| description | An 8T SRAM fabricated in 45 nm SOI CMOS exhibits voltage scalable operation from 1.2 V down to 0.57 V with access times from 400 ps to 3.4 ns. Timing variation and the challenge of low-voltage operation are addressed with an AC-coupled sense amplifier. An area efficient data path is achieved with a regenerative global-bitline scheme. Finally, a data-retention-voltage sensor is developed to predict the mismatch-limited minimum-standby voltage without corrupting the content of the memory. |
| first_indexed | 2024-09-23T11:08:17Z |
| format | Article |
| id | mit-1721.1/62194 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T11:08:17Z |
| publishDate | 2011 |
| publisher | Institute of Electrical and Electronics Engineers |
| record_format | dspace |
| spelling | mit-1721.1/621942022-09-27T17:22:19Z A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS Qazi, Masood Stawiasz, Kevin Chang, Leland Chandrakasan, Anantha P. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology. Microsystems Technology Laboratories Chandrakasan, Anantha P. Qazi, Masood Chandrakasan, Anantha P. An 8T SRAM fabricated in 45 nm SOI CMOS exhibits voltage scalable operation from 1.2 V down to 0.57 V with access times from 400 ps to 3.4 ns. Timing variation and the challenge of low-voltage operation are addressed with an AC-coupled sense amplifier. An area efficient data path is achieved with a regenerative global-bitline scheme. Finally, a data-retention-voltage sensor is developed to predict the mismatch-limited minimum-standby voltage without corrupting the content of the memory. Semiconductor Research Corporation. Center for Circuits and Systems Solutions (Contract 2003-CT-888) 2011-04-11T22:08:57Z 2011-04-11T22:08:57Z 2010-02 Article http://purl.org/eprint/type/ConferencePaper 978-1-4244-6033-5 0193-6530 INSPEC Accession Number: 11204966 http://hdl.handle.net/1721.1/62194 Qazi, M. et al. “A 512kb 8T SRAM Macro Operating down to 0.57V with an AC-coupled Sense Amplifier and Embedded Data-retention-voltage Sensor in 45nm SOI CMOS.” Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International. 2010. 350-351. Copyright © 2010, IEEE https://orcid.org/0000-0002-5977-2748 en_US http://dx.doi.org/10.1109/ISSCC.2010.5433818 IEEE International Solid-State Circuits Conference (ISSCC). Digest of technical papers Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. application/pdf Institute of Electrical and Electronics Engineers IEEE |
| spellingShingle | Qazi, Masood Stawiasz, Kevin Chang, Leland Chandrakasan, Anantha P. A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS |
| title | A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS |
| title_full | A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS |
| title_fullStr | A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS |
| title_full_unstemmed | A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS |
| title_short | A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS |
| title_sort | 512kb 8t sram macro operating down to 0 57v with an ac coupled sense amplifier and embedded data retention voltage sensor in 45nm soi cmos |
| url | http://hdl.handle.net/1721.1/62194 https://orcid.org/0000-0002-5977-2748 |
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