SWIFT: A SWing-reduced Interconnect For a Token-based Network-on-Chip in 90nm CMOS
With the advent of chip multi-processors (CMPs), on-chip networks are critical for providing low-power communications that scale to high core counts. With this motivation, we present a 64-bit, 8×8 mesh Network-on-Chip in 90nm CMOS that: (a) bypasses flit buffering in routers using Token Flow Control...
| Main Authors: | , , , , |
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| Outros autores: | |
| Formato: | Artigo |
| Idioma: | en_US |
| Publicado: |
Institute of Electrical and Electronics Engineers
2011
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| Acceso en liña: | http://hdl.handle.net/1721.1/63111 https://orcid.org/0000-0001-9010-6519 |
| Summary: | With the advent of chip multi-processors (CMPs), on-chip networks are critical for providing low-power communications that scale to high core counts. With this motivation, we present a 64-bit, 8×8 mesh Network-on-Chip in 90nm CMOS that: (a) bypasses flit buffering in routers using Token Flow Control, thereby reducing buffer power along the control path, and (b) uses low-voltage-swing crossbars and links to reduce interconnect energy in the data path. These approaches enable 38% power savings and 39% latency reduction, when compared with an equivalent baseline network. An experimental 2×2 core prototype, operating at 400 MHz, validates our design. |
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