Floorplacement for Partial Reconfigurable FPGA-Based Systems
We presented a resource- and configuration-aware floorplacement framework, tailored for Xilinx Virtex 4 and 5 FPGAs, using an objective function based on external wirelength. Our work aims at identifying groups of Reconfigurable Functional Units that are likely to be configured in the same chip ar...
| Main Authors: | , , , |
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| Other Authors: | |
| Format: | Article |
| Language: | en_US |
| Published: |
Hindawi
2011
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| Online Access: | http://hdl.handle.net/1721.1/65567 |
| _version_ | 1811072565572009984 |
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| author | Montone, A. Santambrogio, Marco Domenico Redaelli, F. Sciuto, D. |
| author2 | Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory |
| author_facet | Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory Montone, A. Santambrogio, Marco Domenico Redaelli, F. Sciuto, D. |
| author_sort | Montone, A. |
| collection | MIT |
| description | We presented a resource- and configuration-aware floorplacement framework, tailored for Xilinx Virtex 4 and 5 FPGAs, using
an objective function based on external wirelength. Our work aims at identifying groups of Reconfigurable Functional Units that
are likely to be configured in the same chip area, identifying these areas based on resource requirements, device capabilities,
and wirelength. Task graphs with few externally connected RRs lead to the biggest decrease, while external wirelength in task
graphs with many externally connected RRs show lower improvement. The proposed approach results, as also demonstrated in
the experimental results section, in a shorter external wirelength (an average reduction of 50%) with respect to purely area-driven
approaches and a highly increased probability of reuse of existing links (90% reduction can be obtained in the best case). |
| first_indexed | 2024-09-23T09:07:57Z |
| format | Article |
| id | mit-1721.1/65567 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T09:07:57Z |
| publishDate | 2011 |
| publisher | Hindawi |
| record_format | dspace |
| spelling | mit-1721.1/655672022-09-26T10:41:55Z Floorplacement for Partial Reconfigurable FPGA-Based Systems Montone, A. Santambrogio, Marco Domenico Redaelli, F. Sciuto, D. Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory Santambrogio, Marco Domenico Santambrogio, Marco Domenico We presented a resource- and configuration-aware floorplacement framework, tailored for Xilinx Virtex 4 and 5 FPGAs, using an objective function based on external wirelength. Our work aims at identifying groups of Reconfigurable Functional Units that are likely to be configured in the same chip area, identifying these areas based on resource requirements, device capabilities, and wirelength. Task graphs with few externally connected RRs lead to the biggest decrease, while external wirelength in task graphs with many externally connected RRs show lower improvement. The proposed approach results, as also demonstrated in the experimental results section, in a shorter external wirelength (an average reduction of 50%) with respect to purely area-driven approaches and a highly increased probability of reuse of existing links (90% reduction can be obtained in the best case). 2011-08-31T15:51:37Z 2011-08-31T15:51:37Z 2011 2010-08 Article http://purl.org/eprint/type/JournalArticle 1687-7209 1687-7195 http://hdl.handle.net/1721.1/65567 Montone, A. et al. “Floorplacement for Partial Reconfigurable FPGA-Based Systems.” International Journal of Reconfigurable Computing 2011 (2011) : 1-12. Copyright © 2011 A. Montone et al. en_US http://dx.doi.org/10.1155/2011/483681 International Journal of Reconfigurable Computing Creative Commons Attribution http://creativecommons.org/licenses/by/2.0/ application/pdf Hindawi Hindawi |
| spellingShingle | Montone, A. Santambrogio, Marco Domenico Redaelli, F. Sciuto, D. Floorplacement for Partial Reconfigurable FPGA-Based Systems |
| title | Floorplacement for Partial Reconfigurable FPGA-Based Systems |
| title_full | Floorplacement for Partial Reconfigurable FPGA-Based Systems |
| title_fullStr | Floorplacement for Partial Reconfigurable FPGA-Based Systems |
| title_full_unstemmed | Floorplacement for Partial Reconfigurable FPGA-Based Systems |
| title_short | Floorplacement for Partial Reconfigurable FPGA-Based Systems |
| title_sort | floorplacement for partial reconfigurable fpga based systems |
| url | http://hdl.handle.net/1721.1/65567 |
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