Scalability of Sub-100 nm InAs HEMTs on InP Substrate for Future Logic Applications
We have experimentally studied the scaling behavior of sub-100-nm InAs high-electron mobility transistors (HEMTs) on InP substrate from the logic operation point of view. These devices have been designed for scalability and combine a thin InAlAs barrier and a thin channel containing a pure InAs subc...
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| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers (IEEE)
2012
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| Online Access: | http://hdl.handle.net/1721.1/71639 |
| _version_ | 1810993042592628736 |
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| author | Kim, Dae-Hyun del Alamo, Jesus A. |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Kim, Dae-Hyun del Alamo, Jesus A. |
| author_sort | Kim, Dae-Hyun |
| collection | MIT |
| description | We have experimentally studied the scaling behavior of sub-100-nm InAs high-electron mobility transistors (HEMTs) on InP substrate from the logic operation point of view. These devices have been designed for scalability and combine a thin InAlAs barrier and a thin channel containing a pure InAs subchannel. InAs HEMTs with gate length down to 40 nm exhibit excellent logic figures of merit, such as I[subscript ON]/I[subscript OFF] = 9 × 10[superscript 4], drain-induced-barrier lowering = 80 mV/V, S = 70 mV/dec, and an estimated logic gate delay of 0.6 ps at V[subscript DS] = 0.5 V. In addition, we have obtained excellent high-frequency operation with L[subscript g] = 40 nm, such as f[subscript T] = 491 GHz and f[subscript max] = 402 GHz at V[subscript DS] = 0.5 V. In spite of the narrow bandgap of InAs subchannel, under the studied conditions, our devices are shown not to suffer from excessive band-to-band tunneling. When benchmarked against state-of-the-art Si devices, 40-nm InAs HEMTs exhibit I[subscript ON] = 0.6 A/μm at I[subscript Leak] = 200 nA/μm. This is about two times higher I[subscript ON] than state-of-the-art high-performance 65-nm nMOSFET with comparable physical gate length and I[subscript Leak]. |
| first_indexed | 2024-09-23T13:19:11Z |
| format | Article |
| id | mit-1721.1/71639 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T13:19:11Z |
| publishDate | 2012 |
| publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| record_format | dspace |
| spelling | mit-1721.1/716392022-10-01T14:28:36Z Scalability of Sub-100 nm InAs HEMTs on InP Substrate for Future Logic Applications Kim, Dae-Hyun del Alamo, Jesus A. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science del Alamo, Jesus A. Kim, Dae-Hyun del Alamo, Jesus A. We have experimentally studied the scaling behavior of sub-100-nm InAs high-electron mobility transistors (HEMTs) on InP substrate from the logic operation point of view. These devices have been designed for scalability and combine a thin InAlAs barrier and a thin channel containing a pure InAs subchannel. InAs HEMTs with gate length down to 40 nm exhibit excellent logic figures of merit, such as I[subscript ON]/I[subscript OFF] = 9 × 10[superscript 4], drain-induced-barrier lowering = 80 mV/V, S = 70 mV/dec, and an estimated logic gate delay of 0.6 ps at V[subscript DS] = 0.5 V. In addition, we have obtained excellent high-frequency operation with L[subscript g] = 40 nm, such as f[subscript T] = 491 GHz and f[subscript max] = 402 GHz at V[subscript DS] = 0.5 V. In spite of the narrow bandgap of InAs subchannel, under the studied conditions, our devices are shown not to suffer from excessive band-to-band tunneling. When benchmarked against state-of-the-art Si devices, 40-nm InAs HEMTs exhibit I[subscript ON] = 0.6 A/μm at I[subscript Leak] = 200 nA/μm. This is about two times higher I[subscript ON] than state-of-the-art high-performance 65-nm nMOSFET with comparable physical gate length and I[subscript Leak]. 2012-07-17T12:36:41Z 2012-07-17T12:36:41Z 2010-06 Article http://purl.org/eprint/type/JournalArticle 0018-9383 1557-9646 http://hdl.handle.net/1721.1/71639 Kim, Dae-Hyun, and Jesús A. del Alamo. “Scalability of Sub-100 Nm InAs HEMTs on InP Substrate for Future Logic Applications.” IEEE Transactions on Electron Devices 57.7 (2010). © Copyright 2012 IEEE en_US http://dx.doi.org/10.1109/ted.2010.2049075 IEEE Transactions on Electron Devices Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. application/pdf Institute of Electrical and Electronics Engineers (IEEE) IEEE |
| spellingShingle | Kim, Dae-Hyun del Alamo, Jesus A. Scalability of Sub-100 nm InAs HEMTs on InP Substrate for Future Logic Applications |
| title | Scalability of Sub-100 nm InAs HEMTs on InP Substrate for Future Logic Applications |
| title_full | Scalability of Sub-100 nm InAs HEMTs on InP Substrate for Future Logic Applications |
| title_fullStr | Scalability of Sub-100 nm InAs HEMTs on InP Substrate for Future Logic Applications |
| title_full_unstemmed | Scalability of Sub-100 nm InAs HEMTs on InP Substrate for Future Logic Applications |
| title_short | Scalability of Sub-100 nm InAs HEMTs on InP Substrate for Future Logic Applications |
| title_sort | scalability of sub 100 nm inas hemts on inp substrate for future logic applications |
| url | http://hdl.handle.net/1721.1/71639 |
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