A Self-Aligned InGaAs HEMT Architecture for Logic Applications
In this paper, we present a novel self-aligned process for future III-V logic FETs. Using this process, we have demonstrated enhancement-mode 90-nm-gate-length InGaAs HEMTs with excellent logic figures of merit. We have carried out a detailed analysis of this device architecture to determine its fut...
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| Formáid: | Alt |
| Teanga: | en_US |
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Institute of Electrical and Electronics Engineers (IEEE)
2012
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| Rochtain ar líne: | http://hdl.handle.net/1721.1/71795 |
| _version_ | 1826217759691767808 |
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| author | Waldron, Niamh Kim, Dae-Hyun del Alamo, Jesus A. |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Waldron, Niamh Kim, Dae-Hyun del Alamo, Jesus A. |
| author_sort | Waldron, Niamh |
| collection | MIT |
| description | In this paper, we present a novel self-aligned process for future III-V logic FETs. Using this process, we have demonstrated enhancement-mode 90-nm-gate-length InGaAs HEMTs with excellent logic figures of merit. We have carried out a detailed analysis of this device architecture to determine its future scaling capabilities. We find that, as the insulator is scaled to achieve enhancement mode, the performance of the device is limited by degradation of the I [subscript ON]/I [subscript OFF] ratio due to gate leakage current. By use of TLM test structures, we have determined that the barrier resistance dominates the source resistance. We use a trilayer TLM model to predict the expected evolution of the contact resistance as it is scaled to realistic VLSI dimensions and find that the current technology results in resistance values that are two orders of magnitude higher than the desired target for sub-22-nm nodes. Using the model, we explore different options for device redesign. Both I [subscript ON]/I [subscript OFF] and source-resistance limitations imply that the use of a high-k gate dielectric will be required for future device implementations. |
| first_indexed | 2024-09-23T17:08:42Z |
| format | Article |
| id | mit-1721.1/71795 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T17:08:42Z |
| publishDate | 2012 |
| publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| record_format | dspace |
| spelling | mit-1721.1/717952022-10-03T10:44:06Z A Self-Aligned InGaAs HEMT Architecture for Logic Applications Waldron, Niamh Kim, Dae-Hyun del Alamo, Jesus A. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science del Alamo, Jesus A. Waldron, Niamh Kim, Dae-Hyun del Alamo, Jesus A. In this paper, we present a novel self-aligned process for future III-V logic FETs. Using this process, we have demonstrated enhancement-mode 90-nm-gate-length InGaAs HEMTs with excellent logic figures of merit. We have carried out a detailed analysis of this device architecture to determine its future scaling capabilities. We find that, as the insulator is scaled to achieve enhancement mode, the performance of the device is limited by degradation of the I [subscript ON]/I [subscript OFF] ratio due to gate leakage current. By use of TLM test structures, we have determined that the barrier resistance dominates the source resistance. We use a trilayer TLM model to predict the expected evolution of the contact resistance as it is scaled to realistic VLSI dimensions and find that the current technology results in resistance values that are two orders of magnitude higher than the desired target for sub-22-nm nodes. Using the model, we explore different options for device redesign. Both I [subscript ON]/I [subscript OFF] and source-resistance limitations imply that the use of a high-k gate dielectric will be required for future device implementations. 2012-07-25T13:15:53Z 2012-07-25T13:15:53Z 2009-12 2009-09 Article http://purl.org/eprint/type/JournalArticle 0018-9383 1557-9646 http://hdl.handle.net/1721.1/71795 Waldron, Niamh, Dae-Hyun Kim, and JesÚs A. del Alamo. “A Self-Aligned InGaAs HEMT Architecture for Logic Applications.” IEEE Transactions on Electron Devices 57.1 (2010): 297–304. © Copyright 2012 IEEE en_US http://dx.doi.org/10.1109/ted.2009.2035031 IEEE Transactions on Electron Devices Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. application/pdf Institute of Electrical and Electronics Engineers (IEEE) IEEE |
| spellingShingle | Waldron, Niamh Kim, Dae-Hyun del Alamo, Jesus A. A Self-Aligned InGaAs HEMT Architecture for Logic Applications |
| title | A Self-Aligned InGaAs HEMT Architecture for Logic Applications |
| title_full | A Self-Aligned InGaAs HEMT Architecture for Logic Applications |
| title_fullStr | A Self-Aligned InGaAs HEMT Architecture for Logic Applications |
| title_full_unstemmed | A Self-Aligned InGaAs HEMT Architecture for Logic Applications |
| title_short | A Self-Aligned InGaAs HEMT Architecture for Logic Applications |
| title_sort | self aligned ingaas hemt architecture for logic applications |
| url | http://hdl.handle.net/1721.1/71795 |
| work_keys_str_mv | AT waldronniamh aselfalignedingaashemtarchitectureforlogicapplications AT kimdaehyun aselfalignedingaashemtarchitectureforlogicapplications AT delalamojesusa aselfalignedingaashemtarchitectureforlogicapplications AT waldronniamh selfalignedingaashemtarchitectureforlogicapplications AT kimdaehyun selfalignedingaashemtarchitectureforlogicapplications AT delalamojesusa selfalignedingaashemtarchitectureforlogicapplications |