A Self-Aligned InGaAs HEMT Architecture for Logic Applications

A Self-Aligned InGaAs HEMT Architecture for Logic Applications

In this paper, we present a novel self-aligned process for future III-V logic FETs. Using this process, we have demonstrated enhancement-mode 90-nm-gate-length InGaAs HEMTs with excellent logic figures of merit. We have carried out a detailed analysis of this device architecture to determine its fut...

Szczegółowa specyfikacja

Opis bibliograficzny
Główni autorzy:	Waldron, Niamh, Kim, Dae-Hyun, del Alamo, Jesus A.
Kolejni autorzy:	Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Format:	Artykuł
Język:	en_US
Wydane:	Institute of Electrical and Electronics Engineers (IEEE) 2012
Dostęp online:	http://hdl.handle.net/1721.1/71795

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