Logic characteristics of 40 nm thin-channel InAs HEMTs
We have experimentally investigated the trade-offs involved in thinning down the channel of III-V FETs with the ultimate goal of enhancing the electrostatic integrity and scalability of these devices. To do so, we have fabricated InAs HEMTs with a channel thickness of t[subscript ch] = 5 nm and we h...
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| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers (IEEE)
2012
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| Online Access: | http://hdl.handle.net/1721.1/71981 |
| _version_ | 1811072248313806848 |
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| author | Kim, Tae-Woo Kim, Dae-Hyun del Alamo, Jesus A. |
| author2 | Massachusetts Institute of Technology. Microsystems Technology Laboratories |
| author_facet | Massachusetts Institute of Technology. Microsystems Technology Laboratories Kim, Tae-Woo Kim, Dae-Hyun del Alamo, Jesus A. |
| author_sort | Kim, Tae-Woo |
| collection | MIT |
| description | We have experimentally investigated the trade-offs involved in thinning down the channel of III-V FETs with the ultimate goal of enhancing the electrostatic integrity and scalability of these devices. To do so, we have fabricated InAs HEMTs with a channel thickness of t[subscript ch] = 5 nm and we have compared them against, InAs HEMTs with t[subscript ch] = 10 nm. The fabricated thin-channel devices exhibit outstanding logic performance and scalability down to 40 nm in gate length. L[subscript g] = 40 nm devices exhibit S = 72 mV/dec, DIBL = 72 mV/V, and I[subscript ON]/I[subscript OFF] = 2.5 × 104, all at V[subscript DS] = 0.5 V. However, there are trade-offs of using a thin channel which manifest themselves in a higher source resistance, lower transconductance, and lower f[subscript T] when compared with InAs HEMTs with t[subscript ch] = 10 nm. |
| first_indexed | 2024-09-23T09:03:00Z |
| format | Article |
| id | mit-1721.1/71981 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T09:03:00Z |
| publishDate | 2012 |
| publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| record_format | dspace |
| spelling | mit-1721.1/719812022-09-26T10:04:23Z Logic characteristics of 40 nm thin-channel InAs HEMTs Kim, Tae-Woo Kim, Dae-Hyun del Alamo, Jesus A. Massachusetts Institute of Technology. Microsystems Technology Laboratories del Alamo, Jesus A. Kim, Tae-Woo del Alamo, Jesus A. We have experimentally investigated the trade-offs involved in thinning down the channel of III-V FETs with the ultimate goal of enhancing the electrostatic integrity and scalability of these devices. To do so, we have fabricated InAs HEMTs with a channel thickness of t[subscript ch] = 5 nm and we have compared them against, InAs HEMTs with t[subscript ch] = 10 nm. The fabricated thin-channel devices exhibit outstanding logic performance and scalability down to 40 nm in gate length. L[subscript g] = 40 nm devices exhibit S = 72 mV/dec, DIBL = 72 mV/V, and I[subscript ON]/I[subscript OFF] = 2.5 × 104, all at V[subscript DS] = 0.5 V. However, there are trade-offs of using a thin channel which manifest themselves in a higher source resistance, lower transconductance, and lower f[subscript T] when compared with InAs HEMTs with t[subscript ch] = 10 nm. Intel Corporation Semiconductor Research Corporation. Center for Materials, Structures and Devices 2012-08-03T15:56:59Z 2012-08-03T15:56:59Z 2010-07 2010-05 Article http://purl.org/eprint/type/ConferencePaper 978-1-4244-5919-3 1092-8669 http://hdl.handle.net/1721.1/71981 Kim, Tae-Woo, Dae-Hyun Kim, and Jesus A. del Alamo. “Logic Characteristics of 40 Nm Thin-channel InAs HEMTs.” 2010 International Conference on Indium Phosphide & Related Materials. IEEE, 2010. 1–4. © Copyright 2010 IEEE en_US http://dx.doi.org/10.1109/ICIPRM.2010.5516257 2010 International Conference on Indium Phosphide & Related Materials Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. application/pdf Institute of Electrical and Electronics Engineers (IEEE) IEEE |
| spellingShingle | Kim, Tae-Woo Kim, Dae-Hyun del Alamo, Jesus A. Logic characteristics of 40 nm thin-channel InAs HEMTs |
| title | Logic characteristics of 40 nm thin-channel InAs HEMTs |
| title_full | Logic characteristics of 40 nm thin-channel InAs HEMTs |
| title_fullStr | Logic characteristics of 40 nm thin-channel InAs HEMTs |
| title_full_unstemmed | Logic characteristics of 40 nm thin-channel InAs HEMTs |
| title_short | Logic characteristics of 40 nm thin-channel InAs HEMTs |
| title_sort | logic characteristics of 40 nm thin channel inas hemts |
| url | http://hdl.handle.net/1721.1/71981 |
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