ATAC: Improving performance and programmability
Given the current trends in multicore scaling, chips with 1000 cores may exist within the next 5 to 10 years. However, their promise of increased performance will only be reached if their inherent scaling and programming challenges are overcome. Meanwhile, recent advances in nanophotonic device manu...
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| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers (IEEE)
2012
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| Online Access: | http://hdl.handle.net/1721.1/72049 https://orcid.org/0000-0002-7015-4262 https://orcid.org/0000-0002-6057-9769 https://orcid.org/0000-0003-1371-7177 |
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| author | Psota, James R. Miller, Jason E. Kurian, George Hoffman, Henry Beckmann, Nathan Zachary Eastep, Jonathan Michael Agarwal, Anant |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Psota, James R. Miller, Jason E. Kurian, George Hoffman, Henry Beckmann, Nathan Zachary Eastep, Jonathan Michael Agarwal, Anant |
| author_sort | Psota, James R. |
| collection | MIT |
| description | Given the current trends in multicore scaling, chips with 1000 cores may exist within the next 5 to 10 years. However, their promise of increased performance will only be reached if their inherent scaling and programming challenges are overcome. Meanwhile, recent advances in nanophotonic device manufacturing are making CMOS-integrated optics a reality-interconnect technology which can provide more bandwidth at lower power than conventional electronics. Perhaps more importantly, optical interconnect also has the potential to enable new, easy-to-use programming models enabled by its inexpensive broadcast mechanism. This paper introduces ATAC, a new manycore architecture that capitalizes on the recent advances in optics to address a number of challenges that future manycore designs will face. The new constraints and opportunities of on-chip optical interconnect are presented and explored in the design of ATAC. Furthermore, this paper discusses ATAC's programming models, and introduces Consumer Tagging, a novel programming model that leverages ATAC's strengths to provide high performance and scalability. |
| first_indexed | 2024-09-23T16:47:57Z |
| format | Article |
| id | mit-1721.1/72049 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T16:47:57Z |
| publishDate | 2012 |
| publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| record_format | dspace |
| spelling | mit-1721.1/720492022-09-29T21:34:46Z ATAC: Improving performance and programmability Psota, James R. Miller, Jason E. Kurian, George Hoffman, Henry Beckmann, Nathan Zachary Eastep, Jonathan Michael Agarwal, Anant Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Agarwal, Anant Psota, James R. Miller, Jason E. Kurian, George Hoffman, Henry Beckmann, Nathan Zachary Eastep, Jonathan Michael Agarwal, Anant Given the current trends in multicore scaling, chips with 1000 cores may exist within the next 5 to 10 years. However, their promise of increased performance will only be reached if their inherent scaling and programming challenges are overcome. Meanwhile, recent advances in nanophotonic device manufacturing are making CMOS-integrated optics a reality-interconnect technology which can provide more bandwidth at lower power than conventional electronics. Perhaps more importantly, optical interconnect also has the potential to enable new, easy-to-use programming models enabled by its inexpensive broadcast mechanism. This paper introduces ATAC, a new manycore architecture that capitalizes on the recent advances in optics to address a number of challenges that future manycore designs will face. The new constraints and opportunities of on-chip optical interconnect are presented and explored in the design of ATAC. Furthermore, this paper discusses ATAC's programming models, and introduces Consumer Tagging, a novel programming model that leverages ATAC's strengths to provide high performance and scalability. 2012-08-08T19:49:50Z 2012-08-08T19:49:50Z 2010-08 2010-05 Article http://purl.org/eprint/type/JournalArticle 978-1-4244-5308-5 978-1-4244-5309-2 http://hdl.handle.net/1721.1/72049 Psota, James et al. “ATAC: Improving performance and programmability with on-chip optical networks.” IEEE, 2010. 3325-3328. ©2010 IEEE https://orcid.org/0000-0002-7015-4262 https://orcid.org/0000-0002-6057-9769 https://orcid.org/0000-0003-1371-7177 en_US http://dx.doi.org/10.1109/ISCAS.2010.5537892 Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS) Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. application/pdf Institute of Electrical and Electronics Engineers (IEEE) IEEE |
| spellingShingle | Psota, James R. Miller, Jason E. Kurian, George Hoffman, Henry Beckmann, Nathan Zachary Eastep, Jonathan Michael Agarwal, Anant ATAC: Improving performance and programmability |
| title | ATAC: Improving performance and programmability |
| title_full | ATAC: Improving performance and programmability |
| title_fullStr | ATAC: Improving performance and programmability |
| title_full_unstemmed | ATAC: Improving performance and programmability |
| title_short | ATAC: Improving performance and programmability |
| title_sort | atac improving performance and programmability |
| url | http://hdl.handle.net/1721.1/72049 https://orcid.org/0000-0002-7015-4262 https://orcid.org/0000-0002-6057-9769 https://orcid.org/0000-0003-1371-7177 |
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