Memory coherence in the age of multicores
As we enter an era of exascale multicores, the question of efficiently supporting a shared memory model has become of paramount importance. On the one hand, programmers demand the convenience of coherent shared memory; on the other, growing core counts place higher demands on the memory subsystem an...
| Main Authors: | , , , |
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| Other Authors: | |
| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers (IEEE)
2012
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| Online Access: | http://hdl.handle.net/1721.1/72582 https://orcid.org/0000-0001-8253-7714 |
| _version_ | 1826208256444334080 |
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| author | Lis, Mieszko Shim, Keun Sup Cho, Myong Hyon Devadas, Srinivas |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Lis, Mieszko Shim, Keun Sup Cho, Myong Hyon Devadas, Srinivas |
| author_sort | Lis, Mieszko |
| collection | MIT |
| description | As we enter an era of exascale multicores, the question of efficiently supporting a shared memory model has become of paramount importance. On the one hand, programmers demand the convenience of coherent shared memory; on the other, growing core counts place higher demands on the memory subsystem and increasing on-chip distances mean that interconnect delays are becoming a significant part of memory access latencies. In this article, we first review the traditional techniques for providing a shared memory abstraction at the hardware level in multicore systems. We describe two new schemes that guarantee coherent shared memory without the complexity and overheads of a cache coherence protocol, namely execution migration and library cache coherence. We compare these approaches using an analytical model based on average memory latency, and give intuition for the strengths and weaknesses of each. Finally, we describe hybrid schemes that combine the strengths of different schemes. |
| first_indexed | 2024-09-23T14:02:40Z |
| format | Article |
| id | mit-1721.1/72582 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T14:02:40Z |
| publishDate | 2012 |
| publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| record_format | dspace |
| spelling | mit-1721.1/725822022-10-01T18:47:40Z Memory coherence in the age of multicores Lis, Mieszko Shim, Keun Sup Cho, Myong Hyon Devadas, Srinivas Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Devadas, Srinivas Lis, Mieszko Shim, Keun Sup Cho, Myong Hyon Devadas, Srinivas As we enter an era of exascale multicores, the question of efficiently supporting a shared memory model has become of paramount importance. On the one hand, programmers demand the convenience of coherent shared memory; on the other, growing core counts place higher demands on the memory subsystem and increasing on-chip distances mean that interconnect delays are becoming a significant part of memory access latencies. In this article, we first review the traditional techniques for providing a shared memory abstraction at the hardware level in multicore systems. We describe two new schemes that guarantee coherent shared memory without the complexity and overheads of a cache coherence protocol, namely execution migration and library cache coherence. We compare these approaches using an analytical model based on average memory latency, and give intuition for the strengths and weaknesses of each. Finally, we describe hybrid schemes that combine the strengths of different schemes. 2012-09-07T19:35:51Z 2012-09-07T19:35:51Z 2011-11 2011-10 Article http://purl.org/eprint/type/ConferencePaper 978-1-4577-1953-0 1063-6404 http://hdl.handle.net/1721.1/72582 Lis, Mieszko et al. “Memory Coherence in the Age of Multicores.” IEEE 29th International Conference on Computer Design 2011 (ICCD). 1–8. https://orcid.org/0000-0001-8253-7714 en_US http://dx.doi.org/10.1109/ICCD.2011.6081367 IEEE 29th International Conference on Computer Design 2011 (ICCD) Creative Commons Attribution-Noncommercial-Share Alike 3.0 http://creativecommons.org/licenses/by-nc-sa/3.0/ application/pdf Institute of Electrical and Electronics Engineers (IEEE) MIT web domain |
| spellingShingle | Lis, Mieszko Shim, Keun Sup Cho, Myong Hyon Devadas, Srinivas Memory coherence in the age of multicores |
| title | Memory coherence in the age of multicores |
| title_full | Memory coherence in the age of multicores |
| title_fullStr | Memory coherence in the age of multicores |
| title_full_unstemmed | Memory coherence in the age of multicores |
| title_short | Memory coherence in the age of multicores |
| title_sort | memory coherence in the age of multicores |
| url | http://hdl.handle.net/1721.1/72582 https://orcid.org/0000-0001-8253-7714 |
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