Thermal considerations for advanced SOI substrates designed for III-V/Si heterointegration
Silicon-on-lattice engineered substrates (SOLES) are SOI substrates with embedded Ge layers that facilitate III-V compound integration for advanced integrated circuits. The new materials integration scheme in SOLES requires the analysis of its thermal stability and diffusion barrier properties. In t...
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| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers (IEEE)
2012
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| Online Access: | http://hdl.handle.net/1721.1/73512 https://orcid.org/0000-0002-1891-1959 |
| _version_ | 1811081607664107520 |
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| author | Bulsara, Mayank Fitzgerald, Eugene A. Yang, N. Liu, W. K. Lubyshev, D. Fastenau, J. M. Wu, Y. Urteaga, M. Ha, W. Bergman, J. Brar, B. Drazek, C. Daval, N. Benaissa, L. Augendre, E. Hoke, William E. LaRoche, J. R. Herrick, K. J. Kazior, T. E. |
| author2 | Massachusetts Institute of Technology. Department of Materials Science and Engineering |
| author_facet | Massachusetts Institute of Technology. Department of Materials Science and Engineering Bulsara, Mayank Fitzgerald, Eugene A. Yang, N. Liu, W. K. Lubyshev, D. Fastenau, J. M. Wu, Y. Urteaga, M. Ha, W. Bergman, J. Brar, B. Drazek, C. Daval, N. Benaissa, L. Augendre, E. Hoke, William E. LaRoche, J. R. Herrick, K. J. Kazior, T. E. |
| author_sort | Bulsara, Mayank |
| collection | MIT |
| description | Silicon-on-lattice engineered substrates (SOLES) are SOI substrates with embedded Ge layers that facilitate III-V compound integration for advanced integrated circuits. The new materials integration scheme in SOLES requires the analysis of its thermal stability and diffusion barrier properties. In this study, we report on the successful monolithic integration of CMOS/III-V transistors with a reduced CMOS thermal budget. We further investigated the ultimate thermal budget limits for the SOLES platform. We demonstrated a new SOLES structure incorporating a SiNx interlayer, which adds greater integration flexibility for future circuit applications. |
| first_indexed | 2024-09-23T11:49:29Z |
| format | Article |
| id | mit-1721.1/73512 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T11:49:29Z |
| publishDate | 2012 |
| publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| record_format | dspace |
| spelling | mit-1721.1/735122022-09-27T22:08:25Z Thermal considerations for advanced SOI substrates designed for III-V/Si heterointegration Bulsara, Mayank Fitzgerald, Eugene A. Yang, N. Liu, W. K. Lubyshev, D. Fastenau, J. M. Wu, Y. Urteaga, M. Ha, W. Bergman, J. Brar, B. Drazek, C. Daval, N. Benaissa, L. Augendre, E. Hoke, William E. LaRoche, J. R. Herrick, K. J. Kazior, T. E. Massachusetts Institute of Technology. Department of Materials Science and Engineering Bulsara, Mayank Fitzgerald, Eugene A. Yang, N. Silicon-on-lattice engineered substrates (SOLES) are SOI substrates with embedded Ge layers that facilitate III-V compound integration for advanced integrated circuits. The new materials integration scheme in SOLES requires the analysis of its thermal stability and diffusion barrier properties. In this study, we report on the successful monolithic integration of CMOS/III-V transistors with a reduced CMOS thermal budget. We further investigated the ultimate thermal budget limits for the SOLES platform. We demonstrated a new SOLES structure incorporating a SiNx interlayer, which adds greater integration flexibility for future circuit applications. United States. Defense Advanced Research Projects Agency (COSMOS Program contract N00014-07-C-0629) 2012-10-01T16:34:32Z 2012-10-01T16:34:32Z 2009-10 Article http://purl.org/eprint/type/ConferencePaper 978-1-42445232-3 http://hdl.handle.net/1721.1/73512 Yang, N. et al. “Thermal Considerations for Advanced SOI Substrates Designed for III-V/Si Heterointegration.” IEEE, 2009. 1–2. © 2009 IEEE. https://orcid.org/0000-0002-1891-1959 en_US http://dx.doi.org/10.1109/SOI.2009.5318745 IEEE International SOI Conference, 2009 Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. application/pdf Institute of Electrical and Electronics Engineers (IEEE) IEEE |
| spellingShingle | Bulsara, Mayank Fitzgerald, Eugene A. Yang, N. Liu, W. K. Lubyshev, D. Fastenau, J. M. Wu, Y. Urteaga, M. Ha, W. Bergman, J. Brar, B. Drazek, C. Daval, N. Benaissa, L. Augendre, E. Hoke, William E. LaRoche, J. R. Herrick, K. J. Kazior, T. E. Thermal considerations for advanced SOI substrates designed for III-V/Si heterointegration |
| title | Thermal considerations for advanced SOI substrates designed for III-V/Si heterointegration |
| title_full | Thermal considerations for advanced SOI substrates designed for III-V/Si heterointegration |
| title_fullStr | Thermal considerations for advanced SOI substrates designed for III-V/Si heterointegration |
| title_full_unstemmed | Thermal considerations for advanced SOI substrates designed for III-V/Si heterointegration |
| title_short | Thermal considerations for advanced SOI substrates designed for III-V/Si heterointegration |
| title_sort | thermal considerations for advanced soi substrates designed for iii v si heterointegration |
| url | http://hdl.handle.net/1721.1/73512 https://orcid.org/0000-0002-1891-1959 |
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