Non-linear operating point statistical analysis for local variations in logic timing at low voltage
For CMOS feature size of 65 nm and below, local (or intra-die or within-die) variations in transistor Vt contribute stochastic variation in logic delay that is a large percentage of the nominal delay. Moreover, when circuits are operated at low voltage (Vdd ¿ 0.5 V), the standard deviation of gate...
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| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers (IEEE)
2012
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| Online Access: | http://hdl.handle.net/1721.1/74144 https://orcid.org/0000-0002-5977-2748 |
| _version_ | 1826194889770008576 |
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| author | Rithe, Rahulkumar Jagdish Gu, Jie Wang, Alice Datla, Satyendra Gammie, Gordon Buss, Dennis Chandrakasan, Anantha P. |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Rithe, Rahulkumar Jagdish Gu, Jie Wang, Alice Datla, Satyendra Gammie, Gordon Buss, Dennis Chandrakasan, Anantha P. |
| author_sort | Rithe, Rahulkumar Jagdish |
| collection | MIT |
| description | For CMOS feature size of 65 nm and below, local (or intra-die or within-die) variations in transistor Vt contribute stochastic variation in logic delay that is a large percentage of the nominal delay. Moreover, when circuits are operated at low voltage (Vdd ¿ 0.5 V), the standard deviation of gate delay becomes comparable to nominal delay, and the Probability Density Function (PDF) of the gate delay is highly non-Gaussian. This paper presents a computationally efficient algorithm for computing the PDF of logic Timing Path (TP) delay, which results from local variations. This approach is called Non-linear Operating Point Analysis for Local Variations (NLOPALV). The approach is implemented using commercial STA tools and integrated into the standard CAD flow using custom scripts. Timing paths from a 28 nm commercial DSP are analyzed using the proposed technique and the performance is observed to be within 5% accuracy compared to SPICE based Monte-Carlo analysis. |
| first_indexed | 2024-09-23T10:03:26Z |
| format | Article |
| id | mit-1721.1/74144 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T10:03:26Z |
| publishDate | 2012 |
| publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| record_format | dspace |
| spelling | mit-1721.1/741442022-09-26T15:26:22Z Non-linear operating point statistical analysis for local variations in logic timing at low voltage Rithe, Rahulkumar Jagdish Gu, Jie Wang, Alice Datla, Satyendra Gammie, Gordon Buss, Dennis Chandrakasan, Anantha P. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Rithe, Rahulkumar Jagdish Chandrakasan, Anantha P. For CMOS feature size of 65 nm and below, local (or intra-die or within-die) variations in transistor Vt contribute stochastic variation in logic delay that is a large percentage of the nominal delay. Moreover, when circuits are operated at low voltage (Vdd ¿ 0.5 V), the standard deviation of gate delay becomes comparable to nominal delay, and the Probability Density Function (PDF) of the gate delay is highly non-Gaussian. This paper presents a computationally efficient algorithm for computing the PDF of logic Timing Path (TP) delay, which results from local variations. This approach is called Non-linear Operating Point Analysis for Local Variations (NLOPALV). The approach is implemented using commercial STA tools and integrated into the standard CAD flow using custom scripts. Timing paths from a 28 nm commercial DSP are analyzed using the proposed technique and the performance is observed to be within 5% accuracy compared to SPICE based Monte-Carlo analysis. Massachusetts Institute of Technology (Presidential Fellowship) 2012-10-19T13:53:03Z 2012-10-19T13:53:03Z 2010-04 2010-03 Article http://purl.org/eprint/type/ConferencePaper 978-1-4244-7054-9 978-3-9810801-6-2 1530-1591 http://hdl.handle.net/1721.1/74144 Rahul Rithe eta l. "Non-linear operating point statistical analysis for local variations in logic timing at low voltage." Design, Automation & Test in Europe Conference & Exhibition, 965 - 968, 2010. © 2010 EDAA https://orcid.org/0000-0002-5977-2748 en_US http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=5456911&contentType=Conference+Publications&searchField%3DSearch_All%26queryText%3DNon-linear+Operating+Point+Statistical+Analysis+for+Local+Variations+in+Logic+Timing+at+Low+Voltage Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2010 Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. application/pdf Institute of Electrical and Electronics Engineers (IEEE) IEEE |
| spellingShingle | Rithe, Rahulkumar Jagdish Gu, Jie Wang, Alice Datla, Satyendra Gammie, Gordon Buss, Dennis Chandrakasan, Anantha P. Non-linear operating point statistical analysis for local variations in logic timing at low voltage |
| title | Non-linear operating point statistical analysis for local variations in logic timing at low voltage |
| title_full | Non-linear operating point statistical analysis for local variations in logic timing at low voltage |
| title_fullStr | Non-linear operating point statistical analysis for local variations in logic timing at low voltage |
| title_full_unstemmed | Non-linear operating point statistical analysis for local variations in logic timing at low voltage |
| title_short | Non-linear operating point statistical analysis for local variations in logic timing at low voltage |
| title_sort | non linear operating point statistical analysis for local variations in logic timing at low voltage |
| url | http://hdl.handle.net/1721.1/74144 https://orcid.org/0000-0002-5977-2748 |
| work_keys_str_mv | AT ritherahulkumarjagdish nonlinearoperatingpointstatisticalanalysisforlocalvariationsinlogictimingatlowvoltage AT gujie nonlinearoperatingpointstatisticalanalysisforlocalvariationsinlogictimingatlowvoltage AT wangalice nonlinearoperatingpointstatisticalanalysisforlocalvariationsinlogictimingatlowvoltage AT datlasatyendra nonlinearoperatingpointstatisticalanalysisforlocalvariationsinlogictimingatlowvoltage AT gammiegordon nonlinearoperatingpointstatisticalanalysisforlocalvariationsinlogictimingatlowvoltage AT bussdennis nonlinearoperatingpointstatisticalanalysisforlocalvariationsinlogictimingatlowvoltage AT chandrakasanananthap nonlinearoperatingpointstatisticalanalysisforlocalvariationsinlogictimingatlowvoltage |