Non-linear operating point statistical analysis for local variations in logic timing at low voltage

Non-linear operating point statistical analysis for local variations in logic timing at low voltage

For CMOS feature size of 65 nm and below, local (or intra-die or within-die) variations in transistor Vt contribute stochastic variation in logic delay that is a large percentage of the nominal delay. Moreover, when circuits are operated at low voltage (Vdd ¿ 0.5 V), the standard deviation of gate...

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Bibliographic Details
Main Authors: Rithe, Rahulkumar Jagdish, Gu, Jie, Wang, Alice, Datla, Satyendra, Gammie, Gordon, Buss, Dennis, Chandrakasan, Anantha P.
Other Authors: Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Format: Article
Language:en_US
Published: Institute of Electrical and Electronics Engineers (IEEE) 2012
Online Access:http://hdl.handle.net/1721.1/74144
https://orcid.org/0000-0002-5977-2748

Internet

http://hdl.handle.net/1721.1/74144
https://orcid.org/0000-0002-5977-2748

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