Non-linear operating point statistical analysis for local variations in logic timing at low voltage
For CMOS feature size of 65 nm and below, local (or intra-die or within-die) variations in transistor Vt contribute stochastic variation in logic delay that is a large percentage of the nominal delay. Moreover, when circuits are operated at low voltage (Vdd ¿ 0.5 V), the standard deviation of gate...
| Main Authors: | , , , , , , |
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| Other Authors: | |
| Format: | Article |
| Language: | en_US |
| Published: |
Institute of Electrical and Electronics Engineers (IEEE)
2012
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| Online Access: | http://hdl.handle.net/1721.1/74144 https://orcid.org/0000-0002-5977-2748 |