Memory Hierarchy Hardware-Software Co-design in Embedded Systems
The memory hierarchy is the main bottleneck in modern computer systems as the gap between the speed of the processor and the memory continues to grow larger. The situation in embedded systems is even worse. The memory hierarchy consumes a large amount of chip area and energy, which are precious reso...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
2004
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| Subjects: | |
| Online Access: | http://hdl.handle.net/1721.1/7427 |
| _version_ | 1811089902063845376 |
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| author | Ge, Zhiguo Lim, H. B. Wong, Weng Fai |
| author_facet | Ge, Zhiguo Lim, H. B. Wong, Weng Fai |
| author_sort | Ge, Zhiguo |
| collection | MIT |
| description | The memory hierarchy is the main bottleneck in modern computer systems as the gap between the speed of the processor and the memory continues to grow larger. The situation in embedded systems is even worse. The memory hierarchy consumes a large amount of chip area and energy, which are precious resources in embedded systems. Moreover, embedded systems have multiple design objectives such as performance, energy consumption, and area, etc.
Customizing the memory hierarchy for specific applications is a very important way to take full advantage of limited resources to maximize the performance. However, the traditional custom memory hierarchy design methodologies are phase-ordered. They separate the application optimization from the memory hierarchy architecture design, which tend to result in local-optimal solutions. In traditional Hardware-Software co-design methodologies, much of the work has focused on utilizing reconfigurable logic to partition the computation. However, utilizing reconfigurable logic to perform the memory hierarchy design is seldom addressed.
In this paper, we propose a new framework for designing memory hierarchy for embedded systems. The framework will take advantage of the flexible reconfigurable logic to customize the memory hierarchy for specific applications. It combines the application optimization and memory hierarchy design together to obtain a global-optimal solution. Using the framework, we performed a case study to design a new software-controlled instruction memory that showed promising potential. |
| first_indexed | 2024-09-23T14:27:05Z |
| format | Article |
| id | mit-1721.1/7427 |
| institution | Massachusetts Institute of Technology |
| language | English |
| last_indexed | 2024-09-23T14:27:05Z |
| publishDate | 2004 |
| record_format | dspace |
| spelling | mit-1721.1/74272019-04-12T08:39:42Z Memory Hierarchy Hardware-Software Co-design in Embedded Systems Ge, Zhiguo Lim, H. B. Wong, Weng Fai Memory hierarchy design embedded systems reconfigurable logic The memory hierarchy is the main bottleneck in modern computer systems as the gap between the speed of the processor and the memory continues to grow larger. The situation in embedded systems is even worse. The memory hierarchy consumes a large amount of chip area and energy, which are precious resources in embedded systems. Moreover, embedded systems have multiple design objectives such as performance, energy consumption, and area, etc. Customizing the memory hierarchy for specific applications is a very important way to take full advantage of limited resources to maximize the performance. However, the traditional custom memory hierarchy design methodologies are phase-ordered. They separate the application optimization from the memory hierarchy architecture design, which tend to result in local-optimal solutions. In traditional Hardware-Software co-design methodologies, much of the work has focused on utilizing reconfigurable logic to partition the computation. However, utilizing reconfigurable logic to perform the memory hierarchy design is seldom addressed. In this paper, we propose a new framework for designing memory hierarchy for embedded systems. The framework will take advantage of the flexible reconfigurable logic to customize the memory hierarchy for specific applications. It combines the application optimization and memory hierarchy design together to obtain a global-optimal solution. Using the framework, we performed a case study to design a new software-controlled instruction memory that showed promising potential. Singapore-MIT Alliance (SMA) 2004-12-13T07:39:07Z 2004-12-13T07:39:07Z 2005-01 Article http://hdl.handle.net/1721.1/7427 en Computer Science (CS); 113322 bytes application/pdf application/pdf |
| spellingShingle | Memory hierarchy design embedded systems reconfigurable logic Ge, Zhiguo Lim, H. B. Wong, Weng Fai Memory Hierarchy Hardware-Software Co-design in Embedded Systems |
| title | Memory Hierarchy Hardware-Software Co-design in Embedded Systems |
| title_full | Memory Hierarchy Hardware-Software Co-design in Embedded Systems |
| title_fullStr | Memory Hierarchy Hardware-Software Co-design in Embedded Systems |
| title_full_unstemmed | Memory Hierarchy Hardware-Software Co-design in Embedded Systems |
| title_short | Memory Hierarchy Hardware-Software Co-design in Embedded Systems |
| title_sort | memory hierarchy hardware software co design in embedded systems |
| topic | Memory hierarchy design embedded systems reconfigurable logic |
| url | http://hdl.handle.net/1721.1/7427 |
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