Platform for monolithic integration of III-V devices with Si CMOS technology
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2012.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2013
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| Online Access: | http://hdl.handle.net/1721.1/76119 |
| _version_ | 1826200259316940800 |
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| author | Pacella, Nan Yang |
| author2 | Eugene A. Fitzgerald. |
| author_facet | Eugene A. Fitzgerald. Pacella, Nan Yang |
| author_sort | Pacella, Nan Yang |
| collection | MIT |
| description | Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2012. |
| first_indexed | 2024-09-23T11:33:44Z |
| format | Thesis |
| id | mit-1721.1/76119 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T11:33:44Z |
| publishDate | 2013 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/761192019-04-12T21:30:30Z Platform for monolithic integration of III-V devices with Si CMOS technology Pacella, Nan Yang Eugene A. Fitzgerald. Massachusetts Institute of Technology. Dept. of Materials Science and Engineering. Massachusetts Institute of Technology. Dept. of Materials Science and Engineering. Materials Science and Engineering. Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2012. Cataloged from PDF version of thesis. Includes bibliographical references (p. 169-165). Monolithic integration of III-V compound semiconductors and Si complementary metal-oxide- semiconductor (CMOS) enables the creation of advanced circuits with new functionalities. In order to merge the two technologies, compatible substrate platforms and processing approaches must be developed. The Silicon on Lattice Engineered Silicon (SOLES) substrate allows monolithic integration. It is a Si substrate with embedded III-V template layer, which supports epitaxial IIIV device growth, consistent with present II-V technology. The structure is capped with a silicon-on-insulator (SOI) layer, which enables processing of CMOS devices. The processes required for fabricating and utilizing SOLES wafers which have Ge or InP as the III-V template layers are explored. Allowable thermal budgets are important to consider because the substrate must withstand the thermal budget of all subsequent device processing steps. The maximum processing temperature of Ge SOLES is found to be limited by its melting point. However, Ge diffuses through the buried Si0 2 and must be contained. Solutions include 1) limiting device processing thermal budgets, 2) improving buried silicon dioxide quality and 3) incorporating a silicon nitride diffusion barrier. InP SOLES substrates are created using wafer bonding and layer transfer of silicon, SOI and InP-on-Si wafers, established using a two-step growth method. Two different InP SOLES structures are demonstrated and their allowable thermal budgets are investigated. The thermal budgets appear to be limited by low quality silicon dioxide used for wafer bonding. For ultimate integration, parallel metallization of the III-V and CMOS devices is sought. A method of making ohmic contact to III-V materials through Si encapsulation layers, using Si CMOS technology, is established. The metallurgies and electrical characteristics of nickel silicide structures on Si/III-V films are investigated and the NiSi/Si/III-V structure is found to be optimal. This structure is composed of a standard NiSi/Si interface and novel Si/III-V interface. Specific contact resistivity of the double hetero-interface stack can be tuned by controlling Si/IIIV band alignments at the epitaxial growth interface. P-type Si/GaAs interfaces and n-type Si/InGaAs interfaces create ohmic contacts with the lowest specific contact resistivity and present viable structures for integration. A Si-encapsulated GaAs/AlGaAs laser with NiSi front-side contact is demonstrated and confirms the feasibility of these contact structures. by Nan Yang Pacella. Ph.D. 2013-01-07T21:22:28Z 2013-01-07T21:22:28Z 2012 2012 Thesis http://hdl.handle.net/1721.1/76119 821059170 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 176 p. application/pdf Massachusetts Institute of Technology |
| spellingShingle | Materials Science and Engineering. Pacella, Nan Yang Platform for monolithic integration of III-V devices with Si CMOS technology |
| title | Platform for monolithic integration of III-V devices with Si CMOS technology |
| title_full | Platform for monolithic integration of III-V devices with Si CMOS technology |
| title_fullStr | Platform for monolithic integration of III-V devices with Si CMOS technology |
| title_full_unstemmed | Platform for monolithic integration of III-V devices with Si CMOS technology |
| title_short | Platform for monolithic integration of III-V devices with Si CMOS technology |
| title_sort | platform for monolithic integration of iii v devices with si cmos technology |
| topic | Materials Science and Engineering. |
| url | http://hdl.handle.net/1721.1/76119 |
| work_keys_str_mv | AT pacellananyang platformformonolithicintegrationofiiivdeviceswithsicmostechnology |