Advanced modeling of planarization processes for integrated circuit fabrication
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2013
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| Online Access: | http://hdl.handle.net/1721.1/78446 |
| _version_ | 1811079746536079360 |
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| author | Fan, Wei, Ph. D. Massachusetts Institute of Technology |
| author2 | Duane S. Boning. |
| author_facet | Duane S. Boning. Fan, Wei, Ph. D. Massachusetts Institute of Technology |
| author_sort | Fan, Wei, Ph. D. Massachusetts Institute of Technology |
| collection | MIT |
| description | Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012. |
| first_indexed | 2024-09-23T11:19:54Z |
| format | Thesis |
| id | mit-1721.1/78446 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T11:19:54Z |
| publishDate | 2013 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/784462019-04-10T23:07:30Z Advanced modeling of planarization processes for integrated circuit fabrication Fan, Wei, Ph. D. Massachusetts Institute of Technology Duane S. Boning. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012. Cataloged from PDF version of thesis. Includes bibliographical references (p. 215-225). Planarization processes are a key enabling technology for continued performance and density improvements in integrated circuits (ICs). Dielectric material planarization is widely used in front-end-of-line (FEOL) processing for device isolation and in back-end-of-line (BEOL) processing for interconnection. This thesis studies the physical mechanisms and variations in the planarization using chemical mechanical polishing (CMP). The major achievement and contribution of this work is a systematic methodology to physically model and characterize the non-uniformities in the CMP process. To characterize polishing mechanisms at different length scales, physical CMP models are developed in three levels: wafer-level, die-level and particle-level. The wafer-level model investigates the CMP tool effects on wafer-level pressure non-uniformity. The die-level model is developed to study chip-scale non-uniformity induced by layout pattern density dependence and CMP pad properties. The particle-level model focuses on the contact mechanism between pad asperities and the wafer. Two model integration approaches are proposed to connect wafer-level and particle-level models to the die-level model, so that CMP system impacts on die-level uniformity and feature size dependence are considered. The models are applied to characterize and simulate CMP processes by fitting polishing experiment data and extracting physical model parameters. A series of physical measurement approaches are developed to characterize CMP pad properties and verify physical model assumptions. Pad asperity modulus and characteristic asperity height are measured by nanoindentation and microprofilometry, respectively. Pad aging effect is investigated by comparing physical measurement results at different pad usage stages. Results show that in-situ conditioning keeps pad surface properties consistent to perform polishing up to 16 hours, even in the face of substantial pad wear during extended polishing. The CMP mechanisms identified from modeling and physical characterization are applied to explore an alternative polishing process, referred to as pad-in-a-bottle (PIB). A critical challenge related to applied pressure using pad-in-a-bottle polishing is predicted. by Wei Fan. Ph.D. 2013-04-12T19:24:41Z 2013-04-12T19:24:41Z 2012 2012 Thesis http://hdl.handle.net/1721.1/78446 831578259 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 225 p. application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Fan, Wei, Ph. D. Massachusetts Institute of Technology Advanced modeling of planarization processes for integrated circuit fabrication |
| title | Advanced modeling of planarization processes for integrated circuit fabrication |
| title_full | Advanced modeling of planarization processes for integrated circuit fabrication |
| title_fullStr | Advanced modeling of planarization processes for integrated circuit fabrication |
| title_full_unstemmed | Advanced modeling of planarization processes for integrated circuit fabrication |
| title_short | Advanced modeling of planarization processes for integrated circuit fabrication |
| title_sort | advanced modeling of planarization processes for integrated circuit fabrication |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/78446 |
| work_keys_str_mv | AT fanweiphdmassachusettsinstituteoftechnology advancedmodelingofplanarizationprocessesforintegratedcircuitfabrication |