Scalable reconfigurable computing leveraging latency-insensitive channels
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2013
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| Online Access: | http://hdl.handle.net/1721.1/79212 |
| _version_ | 1826205872800399360 |
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| author | Fleming, Kermin Elliott, Jr |
| author2 | Arvind and Joel S. Emer. |
| author_facet | Arvind and Joel S. Emer. Fleming, Kermin Elliott, Jr |
| author_sort | Fleming, Kermin Elliott, Jr |
| collection | MIT |
| description | Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013. |
| first_indexed | 2024-09-23T13:20:27Z |
| format | Thesis |
| id | mit-1721.1/79212 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T13:20:27Z |
| publishDate | 2013 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/792122019-04-10T23:07:33Z Scalable reconfigurable computing leveraging latency-insensitive channels Fleming, Kermin Elliott, Jr Arvind and Joel S. Emer. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013. Cataloged from PDF version of thesis. Includes bibliographical references (p. 190-197). Traditionally, FPGAs have been confined to the limited role of small, low-volume ASIC replacements and as circuit emulators. However, continued Moore's law scaling has given FPGAs new life as accelerators for applications that map well to fine-grained parallel substrates. Examples of such applications include processor modelling, compression, and digital signal processing. Although FPGAs continue to increase in size, some interesting designs still fail to fit in to a single FPGA. Many tools exist that partition RTL descriptions across FPGAs. Unfortunately, existing tools have low performance due to the inefficiency of maintaining the cycle-by-cycle behavior of RTL among discrete FPGAs. These tools are unsuitable for use in FPGA program acceleration, as the purpose of an accelerator is to make applications run faster. This thesis presents latency-insensitive channels, a language-level mechanism by which programmers express points in their their design at which the cycle-by-cycle behavior of the design may be modified by the compiler. By decoupling the timing of portions of the RTL from the high-level function of the program, designs may be mapped to multiple FPGAs without suffering the performance degradation observed in existing tools. This thesis demonstrates, using a diverse set of large designs, that FPGA programs described in terms of latency-insensitive channels obtain significant gains in design feasibility, compilation time, and run-time when mapped to multiple FPGAs. by Kermin Elliott Fleming, Jr. Ph.D. 2013-06-17T19:47:56Z 2013-06-17T19:47:56Z 2013 2013 Thesis http://hdl.handle.net/1721.1/79212 844752850 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 197 p. application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Fleming, Kermin Elliott, Jr Scalable reconfigurable computing leveraging latency-insensitive channels |
| title | Scalable reconfigurable computing leveraging latency-insensitive channels |
| title_full | Scalable reconfigurable computing leveraging latency-insensitive channels |
| title_fullStr | Scalable reconfigurable computing leveraging latency-insensitive channels |
| title_full_unstemmed | Scalable reconfigurable computing leveraging latency-insensitive channels |
| title_short | Scalable reconfigurable computing leveraging latency-insensitive channels |
| title_sort | scalable reconfigurable computing leveraging latency insensitive channels |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/79212 |
| work_keys_str_mv | AT flemingkerminelliottjr scalablereconfigurablecomputingleveraginglatencyinsensitivechannels |