High Performance Mixed Signal Circuits Enabled by the Direct Monolithic Heterogeneous Integration of InP HBT and Si CMOS on a Silicon Substrate
We present recent results on the direct heterogeneous integration of InP HBTs and Si CMOS on a silicon template wafer or SOLES (Silicon On Lattice Engineered Substrate). InP HBTs whose performance are comparable to HBTs on the native InP substrates have been repeatedly achieved. 100% heterogeneous i...
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| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers
2013
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| Online Access: | http://hdl.handle.net/1721.1/81316 https://orcid.org/0000-0002-1891-1959 |
| _version_ | 1826206233824067584 |
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| author | Kazior, T. E. LaRoche, J. R. Urteaga, M. Bergman, J. Choe, M. J. Lee, K. J. Seong, T. Seo, M. Yen, A. Lubyshev, D. Fastenau, J. M. Liu, W. K. Smith, D. Clark, D. Thompson, R. Bulsara, Mayank Fitzgerald, Eugene A. Drazek, C. Guiot, E. |
| author2 | MIT Materials Research Laboratory |
| author_facet | MIT Materials Research Laboratory Kazior, T. E. LaRoche, J. R. Urteaga, M. Bergman, J. Choe, M. J. Lee, K. J. Seong, T. Seo, M. Yen, A. Lubyshev, D. Fastenau, J. M. Liu, W. K. Smith, D. Clark, D. Thompson, R. Bulsara, Mayank Fitzgerald, Eugene A. Drazek, C. Guiot, E. |
| author_sort | Kazior, T. E. |
| collection | MIT |
| description | We present recent results on the direct heterogeneous integration of InP HBTs and Si CMOS on a silicon template wafer or SOLES (Silicon On Lattice Engineered Substrate). InP HBTs whose performance are comparable to HBTs on the native InP substrates have been repeatedly achieved. 100% heterogeneous interconnect yield has been achieved on daisy chain test structures with CMOS-InP HBT spacing (interconnect length) as small as 2.5um. In DARPA COSMOS Phase 1 we designed and fabricated a differential amplifier that met the program Go/NoGo metrics with first pass design success. As the COSMOS Phase 2 demonstration vehicle we designed and fabricated a low power dissipation, high resolution, 500MHz bandwidth digital-to-analog converter (DAC). |
| first_indexed | 2024-09-23T13:26:12Z |
| format | Article |
| id | mit-1721.1/81316 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T13:26:12Z |
| publishDate | 2013 |
| publisher | Institute of Electrical and Electronics Engineers |
| record_format | dspace |
| spelling | mit-1721.1/813162022-09-28T14:10:15Z High Performance Mixed Signal Circuits Enabled by the Direct Monolithic Heterogeneous Integration of InP HBT and Si CMOS on a Silicon Substrate Kazior, T. E. LaRoche, J. R. Urteaga, M. Bergman, J. Choe, M. J. Lee, K. J. Seong, T. Seo, M. Yen, A. Lubyshev, D. Fastenau, J. M. Liu, W. K. Smith, D. Clark, D. Thompson, R. Bulsara, Mayank Fitzgerald, Eugene A. Drazek, C. Guiot, E. MIT Materials Research Laboratory Massachusetts Institute of Technology. Department of Materials Science and Engineering Bulsara, Mayank Fitzgerald, Eugene A. We present recent results on the direct heterogeneous integration of InP HBTs and Si CMOS on a silicon template wafer or SOLES (Silicon On Lattice Engineered Substrate). InP HBTs whose performance are comparable to HBTs on the native InP substrates have been repeatedly achieved. 100% heterogeneous interconnect yield has been achieved on daisy chain test structures with CMOS-InP HBT spacing (interconnect length) as small as 2.5um. In DARPA COSMOS Phase 1 we designed and fabricated a differential amplifier that met the program Go/NoGo metrics with first pass design success. As the COSMOS Phase 2 demonstration vehicle we designed and fabricated a low power dissipation, high resolution, 500MHz bandwidth digital-to-analog converter (DAC). United States. Defense Advanced Research Projects Agency (DARPA COSMOS Program (Contract Number N00014-07-C-0629)) 2013-10-04T15:49:21Z 2013-10-04T15:49:21Z 2010-10 Article http://purl.org/eprint/type/ConferencePaper 978-1-4244-7437-0 978-1-4244-7436-3 INSPEC Accession Number: 11630792 http://hdl.handle.net/1721.1/81316 Kazior, T. E., J. R. LaRoche, M. Urteaga, J. Bergman, M. J. Choe, K. J. Lee, T. Seong, et al. “High Performance Mixed Signal Circuits Enabled by the Direct Monolithic Heterogeneous Integration of InP HBT and Si CMOS on a Silicon Substrate.” In 2010 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), Monterey, CA, USA, 3-6 October 2010, 1-4. Institute of Electrical and Electronics Engineers, 2010. © Copyright 2010 IEEE. https://orcid.org/0000-0002-1891-1959 en_US http://dx.doi.org/10.1109/CSICS.2010.5619670 2010 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. application/pdf Institute of Electrical and Electronics Engineers IEEE |
| spellingShingle | Kazior, T. E. LaRoche, J. R. Urteaga, M. Bergman, J. Choe, M. J. Lee, K. J. Seong, T. Seo, M. Yen, A. Lubyshev, D. Fastenau, J. M. Liu, W. K. Smith, D. Clark, D. Thompson, R. Bulsara, Mayank Fitzgerald, Eugene A. Drazek, C. Guiot, E. High Performance Mixed Signal Circuits Enabled by the Direct Monolithic Heterogeneous Integration of InP HBT and Si CMOS on a Silicon Substrate |
| title | High Performance Mixed Signal Circuits Enabled by the Direct Monolithic Heterogeneous Integration of InP HBT and Si CMOS on a Silicon Substrate |
| title_full | High Performance Mixed Signal Circuits Enabled by the Direct Monolithic Heterogeneous Integration of InP HBT and Si CMOS on a Silicon Substrate |
| title_fullStr | High Performance Mixed Signal Circuits Enabled by the Direct Monolithic Heterogeneous Integration of InP HBT and Si CMOS on a Silicon Substrate |
| title_full_unstemmed | High Performance Mixed Signal Circuits Enabled by the Direct Monolithic Heterogeneous Integration of InP HBT and Si CMOS on a Silicon Substrate |
| title_short | High Performance Mixed Signal Circuits Enabled by the Direct Monolithic Heterogeneous Integration of InP HBT and Si CMOS on a Silicon Substrate |
| title_sort | high performance mixed signal circuits enabled by the direct monolithic heterogeneous integration of inp hbt and si cmos on a silicon substrate |
| url | http://hdl.handle.net/1721.1/81316 https://orcid.org/0000-0002-1891-1959 |
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