Characterization of bonded copper interconnects for three-dimensional integrated circuits
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2002.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2005
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| Online Access: | http://hdl.handle.net/1721.1/8428 |
| _version_ | 1811072230534152192 |
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| author | Tadepalli, Rajappa, 1979- |
| author2 | Carl V. Thompson. |
| author_facet | Carl V. Thompson. Tadepalli, Rajappa, 1979- |
| author_sort | Tadepalli, Rajappa, 1979- |
| collection | MIT |
| description | Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2002. |
| first_indexed | 2024-09-23T09:02:42Z |
| format | Thesis |
| id | mit-1721.1/8428 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T09:02:42Z |
| publishDate | 2005 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/84282019-04-10T20:23:25Z Characterization of bonded copper interconnects for three-dimensional integrated circuits Characterization of bonded copper interconnects for 3D ICs Tadepalli, Rajappa, 1979- Carl V. Thompson. Massachusetts Institute of Technology. Dept. of Materials Science and Engineering. Massachusetts Institute of Technology. Dept. of Materials Science and Engineering. Materials Science and Engineering. Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2002. Includes bibliographical references (leaves 52-54). The unprecedented growth of the semiconductor industry is demanding ultra large-scale integrated (ULSI) circuits with increasing performance at minimum cost and power dissipation. As the critical dimensions in ULSI design continue to shrink, system performance of integrated circuits will be increasingly dominated by interconnect delay. Three-dimensional (3-D) ICs can reduce interconnect delay problems by offering flexibility in system design, placement and routing. 3-D ICs can be formed by vertical integration of multiple device layers using wafer bonding, recrystallization or selective epitaxial growth. The flexibility to place devices along the vertical dimension allows higher device density and reduced total interconnect lengths in 3-D ICs. One approach to fabrication of 3D integrated circuits is to bond previously-processed device layers using metal-metal bonds that also serve as layer-to-layer interconnects. Evaluation of the feasibility of wafer bonding for 3-D integration relies on our ability to characterize bonded interconnects. The reliability of devices containing multi-layer thin film structures is strongly influenced by the adhesion properties of the many interfaces present. Interface fracture failure is highly likely given the high thermal stresses developed during processing and also during service. A four-point bend test technique has been used to evaluate the strength of Cu-Cu bonds. Test structures were fabricated by bonding wafers containing copper lines (with Ta barrier) that were patterned on silicon dioxide. Tests on the thermocompression-bonded copper lines yielded reproducible fracture toughness values (1-10 J/m2 ) for bonds created at 300°C-400°C. The effect of process parameters on bond strength was studied. It was found that surface copper oxide removal prior to bonding using a forming gas purge (95%Ar-5%H2 ) resulted in higher toughness values and lesser variations compared to a N2 purge. Also, bond strength was found to increase with increasing bonding temperature. Thicker bonded films resulted in stronger bonds. Interface failure was found to be most likely at the Cu-Cu and Ta-Silicon dioxide interfaces. The results obtained from different process conditions were used to optimize the bonding process. by Rajappa Tadepalli. S.M. 2005-08-23T20:06:23Z 2005-08-23T20:06:23Z 2002 2002 Thesis http://hdl.handle.net/1721.1/8428 50633291 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 54 leaves 4394626 bytes 4394384 bytes application/pdf application/pdf application/pdf Massachusetts Institute of Technology |
| spellingShingle | Materials Science and Engineering. Tadepalli, Rajappa, 1979- Characterization of bonded copper interconnects for three-dimensional integrated circuits |
| title | Characterization of bonded copper interconnects for three-dimensional integrated circuits |
| title_full | Characterization of bonded copper interconnects for three-dimensional integrated circuits |
| title_fullStr | Characterization of bonded copper interconnects for three-dimensional integrated circuits |
| title_full_unstemmed | Characterization of bonded copper interconnects for three-dimensional integrated circuits |
| title_short | Characterization of bonded copper interconnects for three-dimensional integrated circuits |
| title_sort | characterization of bonded copper interconnects for three dimensional integrated circuits |
| topic | Materials Science and Engineering. |
| url | http://hdl.handle.net/1721.1/8428 |
| work_keys_str_mv | AT tadepallirajappa1979 characterizationofbondedcopperinterconnectsforthreedimensionalintegratedcircuits AT tadepallirajappa1979 characterizationofbondedcopperinterconnectsfor3dics |