Spinal codes
Spinal codes are a new class of rateless codes that enable wireless networks to cope with time-varying channel conditions in a natural way, without requiring any explicit bit rate selection. The key idea in the code is the sequential application of a pseudo-random hash function to the message bits t...
| Autores principales: | , , , , |
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| Otros Autores: | |
| Formato: | Artículo |
| Lenguaje: | en_US |
| Publicado: |
Association for Computing Machinery
2014
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| Acceso en línea: | http://hdl.handle.net/1721.1/85938 https://orcid.org/0000-0002-6465-7023 https://orcid.org/0000-0002-4566-771X https://orcid.org/0000-0003-0737-3259 https://orcid.org/0000-0002-1455-9652 |
| Sumario: | Spinal codes are a new class of rateless codes that enable wireless networks to cope with time-varying channel conditions in a natural way, without requiring any explicit bit rate selection. The key idea in the code is the sequential application of a pseudo-random hash function to the message bits to produce a sequence of coded symbols for transmission. This encoding ensures that two input messages that differ in even one bit lead to very different coded sequences after the point at which they differ, providing good resilience to noise and bit errors. To decode spinal codes, this paper develops an approximate maximum-likelihood decoder, called the bubble decoder, which runs in time polynomial in the message size and achieves the Shannon capacity over both additive white Gaussian noise (AWGN) and binary symmetric channel (BSC) models. Experimental results obtained from a software implementation of a linear-time decoder show that spinal codes achieve higher throughput than fixed-rate LDPC codes, rateless Raptor codes, and the layered rateless coding approach of Strider, across a range of channel conditions and message sizes. An early hardware prototype that can decode at 10 Mbits/s in FPGA demonstrates that spinal codes are a practical construction. |
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