The locality-aware adaptive cache coherence protocol
Next generation multicore applications will process massive amounts of data with significant sharing. Data movement and management impacts memory access latency and consumes power. Therefore, harnessing data locality is of fundamental importance in future processors. We propose a scalable, efficient...
| Main Authors: | , , |
|---|---|
| Other Authors: | |
| Format: | Article |
| Language: | en_US |
| Published: |
Association for Computing Machinery (ACM)
2014
|
| Online Access: | http://hdl.handle.net/1721.1/86168 https://orcid.org/0000-0001-8253-7714 |
| _version_ | 1826198315579998208 |
|---|---|
| author | Kurian, George Khan, Omer Devadas, Srinivas |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Kurian, George Khan, Omer Devadas, Srinivas |
| author_sort | Kurian, George |
| collection | MIT |
| description | Next generation multicore applications will process massive amounts of data with significant sharing. Data movement and management impacts memory access latency and consumes power. Therefore, harnessing data locality is of fundamental importance in future processors. We propose a scalable, efficient shared memory cache coherence protocol that enables seamless adaptation between private and logically shared caching of on-chip data at the fine granularity of cache lines. Our data-centric approach relies on in-hardware yet low-overhead runtime profiling of the locality of each cache line and only allows private caching for data blocks with high spatio-temporal locality. This allows us to better exploit the private caches and enable low-latency, low-energy memory access, while retaining the convenience of shared memory. On a set of parallel benchmarks, our low-overhead locality-aware mechanisms reduce the overall energy by 25% and completion time by 15% in an NoC-based multicore with the Reactive-NUCA on-chip cache organization and the ACKwise limited directory-based coherence protocol. |
| first_indexed | 2024-09-23T11:02:56Z |
| format | Article |
| id | mit-1721.1/86168 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T11:02:56Z |
| publishDate | 2014 |
| publisher | Association for Computing Machinery (ACM) |
| record_format | dspace |
| spelling | mit-1721.1/861682022-09-27T16:43:59Z The locality-aware adaptive cache coherence protocol Kurian, George Khan, Omer Devadas, Srinivas Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Kurian, George Devadas, Srinivas Next generation multicore applications will process massive amounts of data with significant sharing. Data movement and management impacts memory access latency and consumes power. Therefore, harnessing data locality is of fundamental importance in future processors. We propose a scalable, efficient shared memory cache coherence protocol that enables seamless adaptation between private and logically shared caching of on-chip data at the fine granularity of cache lines. Our data-centric approach relies on in-hardware yet low-overhead runtime profiling of the locality of each cache line and only allows private caching for data blocks with high spatio-temporal locality. This allows us to better exploit the private caches and enable low-latency, low-energy memory access, while retaining the convenience of shared memory. On a set of parallel benchmarks, our low-overhead locality-aware mechanisms reduce the overall energy by 25% and completion time by 15% in an NoC-based multicore with the Reactive-NUCA on-chip cache organization and the ACKwise limited directory-based coherence protocol. United States. Defense Advanced Research Projects Agency. The Ubiquitous High Performance Computing Program 2014-04-14T18:53:37Z 2014-04-14T18:53:37Z 2013-06 Article http://purl.org/eprint/type/ConferencePaper 9781450320795 http://hdl.handle.net/1721.1/86168 George Kurian, Omer Khan, and Srinivas Devadas. 2013. The locality-aware adaptive cache coherence protocol. SIGARCH Comput. Archit. News 41, 3 (June 2013), 523-534. https://orcid.org/0000-0001-8253-7714 en_US http://dx.doi.org/10.1145/2485922.2485967 Proceedings of the 40th Annual International Symposium on Computer Architecture (ISCA '13) Creative Commons Attribution-Noncommercial-Share Alike http://creativecommons.org/licenses/by-nc-sa/4.0/ application/pdf Association for Computing Machinery (ACM) Other univ. web domain |
| spellingShingle | Kurian, George Khan, Omer Devadas, Srinivas The locality-aware adaptive cache coherence protocol |
| title | The locality-aware adaptive cache coherence protocol |
| title_full | The locality-aware adaptive cache coherence protocol |
| title_fullStr | The locality-aware adaptive cache coherence protocol |
| title_full_unstemmed | The locality-aware adaptive cache coherence protocol |
| title_short | The locality-aware adaptive cache coherence protocol |
| title_sort | locality aware adaptive cache coherence protocol |
| url | http://hdl.handle.net/1721.1/86168 https://orcid.org/0000-0001-8253-7714 |
| work_keys_str_mv | AT kuriangeorge thelocalityawareadaptivecachecoherenceprotocol AT khanomer thelocalityawareadaptivecachecoherenceprotocol AT devadassrinivas thelocalityawareadaptivecachecoherenceprotocol AT kuriangeorge localityawareadaptivecachecoherenceprotocol AT khanomer localityawareadaptivecachecoherenceprotocol AT devadassrinivas localityawareadaptivecachecoherenceprotocol |