A low-power reconfigurable analog-to-digital converter
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2005
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| Online Access: | http://hdl.handle.net/1721.1/8701 |
| _version_ | 1826211796497727488 |
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| author | Gulati, Kush |
| author2 | Hae-Seung (Harry) Lee. |
| author_facet | Hae-Seung (Harry) Lee. Gulati, Kush |
| author_sort | Gulati, Kush |
| collection | MIT |
| description | Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001. |
| first_indexed | 2024-09-23T15:11:32Z |
| format | Thesis |
| id | mit-1721.1/8701 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T15:11:32Z |
| publishDate | 2005 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/87012019-04-11T03:17:58Z A low-power reconfigurable analog-to-digital converter Gulati, Kush Hae-Seung (Harry) Lee. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001. Includes bibliographical references (p. 197-200). This thesis presents the concept, theory and design of a low power CMOS analog-to-digital converter that can digitize signals over a wide range of bandwidth and resolution with adaptive power consumption. The converter achieves the wide operating range by reconfiguring (1) its architecture between pipeline and delta-sigma modes (2) by varying its circuit parameters such as size of capacitors, length of pipeline, oversampling ratio, among others and (3) by varying the bias currents of the opamps in proportion with converter sampling frequency, accomplished through the use of a phase-locked loop. Target input signals for this ADC include high frequency and moderate resolution signals such as video and low I.F. in radio Receivers, low frequency and high resolution signals from seismic sensors and MEMs devices, and others that fall in between these extremes such as audio, voice and general purpose data-acquisition. This converter also incorporates several power reducing features such as thermal noise limited design, global converter chopping in the pipeline mode, opamp scaling, opamp sharing between consecutive stages in the pipeline mode, an opamp chopping technique in the delta-sigma mode, and other design techniques. The opamp chopping technique achieves faster closed-loop settling time and lower thermal noise than conventional design. (cont.) At a converter power supply at 3.3V, the converter achieves a bandwidth range of 0-10MHz over a resolution range of 6 -16 bits, and parameter reconfiguration time of 12 clock cycles. Its PLL lock range is measured at 20KHz to 40MHz. In the delta-sigma mode, it achieves a maximum SNR of 94dB and second and third harmonic distortions of 102dB and 95dB, respectively at 10MHz clock frequency, 9.4KHz bandwidth, and 17.6mW power. In the pipeline mode, it achieves a maximum DNL and INL of +/-0.55LSBs and +/-0.82LSBs, respectively, at 11-bits of resolution, at a clock frequency of 2.6MHz and 1MHz tone with 24.6mW of power. by Kush Gulati. Ph.D. 2005-08-23T22:28:35Z 2005-08-23T22:28:35Z 2001 2001 Thesis http://hdl.handle.net/1721.1/8701 49839428 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 200 p. 15127453 bytes 15127213 bytes application/pdf application/pdf application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Gulati, Kush A low-power reconfigurable analog-to-digital converter |
| title | A low-power reconfigurable analog-to-digital converter |
| title_full | A low-power reconfigurable analog-to-digital converter |
| title_fullStr | A low-power reconfigurable analog-to-digital converter |
| title_full_unstemmed | A low-power reconfigurable analog-to-digital converter |
| title_short | A low-power reconfigurable analog-to-digital converter |
| title_sort | low power reconfigurable analog to digital converter |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/8701 |
| work_keys_str_mv | AT gulatikush alowpowerreconfigurableanalogtodigitalconverter AT gulatikush lowpowerreconfigurableanalogtodigitalconverter |