Architectural implications of bit-level computation in communication applications
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.
मुख्य लेखक: | |
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अन्य लेखक: | |
स्वरूप: | थीसिस |
भाषा: | eng |
प्रकाशित: |
Massachusetts Institute of Technology
2014
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विषय: | |
ऑनलाइन पहुंच: | http://hdl.handle.net/1721.1/87324 |