A comparative analysis of physical-layer rateless coding architectures
Thesis: S.M. in Electrical Engineering, Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.
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| Other Authors: | |
| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2014
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| Online Access: | http://hdl.handle.net/1721.1/90140 |
| _version_ | 1826216518892912640 |
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| author | Romero, David Luis |
| author2 | Gregory W. Wornell and Adam R. Margetts. |
| author_facet | Gregory W. Wornell and Adam R. Margetts. Romero, David Luis |
| author_sort | Romero, David Luis |
| collection | MIT |
| description | Thesis: S.M. in Electrical Engineering, Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014. |
| first_indexed | 2024-09-23T16:48:39Z |
| format | Thesis |
| id | mit-1721.1/90140 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T16:48:39Z |
| publishDate | 2014 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/901402019-04-11T05:43:17Z A comparative analysis of physical-layer rateless coding architectures Romero, David Luis Gregory W. Wornell and Adam R. Margetts. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis: S.M. in Electrical Engineering, Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014. 21 Cataloged from PDF version of thesis. Includes bibliographical references (pages 113-114). An analysis of rateless codes implemented at the physical layer is developed. Our model takes into account two aspects of practical communication system design that are abstracted away in many existing works on the subject. In particular, our model assumes that : (1) practical error detection methods are used to determine when to terminate decoding; and (2) performance and reliability as observed at the transport layer are the metrics of interest. Within the context of these assumptions, we then evaluate two recently proposed high-performing rateless codes. Using our analysis to guide an empirical study, the process of selecting the best rateless code for a given set of system constraints is illustrated. by David Luis Romero. S.M. in Electrical Engineering 2014-09-19T21:42:06Z 2014-09-19T21:42:06Z 2014 2014 Thesis http://hdl.handle.net/1721.1/90140 890152009 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 115 pages application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Romero, David Luis A comparative analysis of physical-layer rateless coding architectures |
| title | A comparative analysis of physical-layer rateless coding architectures |
| title_full | A comparative analysis of physical-layer rateless coding architectures |
| title_fullStr | A comparative analysis of physical-layer rateless coding architectures |
| title_full_unstemmed | A comparative analysis of physical-layer rateless coding architectures |
| title_short | A comparative analysis of physical-layer rateless coding architectures |
| title_sort | comparative analysis of physical layer rateless coding architectures |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/90140 |
| work_keys_str_mv | AT romerodavidluis acomparativeanalysisofphysicallayerratelesscodingarchitectures AT romerodavidluis comparativeanalysisofphysicallayerratelesscodingarchitectures |