SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects
A 64-bit, 8 × 8 mesh network-on-chip (NoC) is presented that uses both new architectural and circuit design techniques to improve on-chip network energy-efficiency, latency, and throughput. First, we propose token flow control, which enables bypassing of flit buffering in routers, thereby reducing b...
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| Other Authors: | |
| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers (IEEE)
2014
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| Online Access: | http://hdl.handle.net/1721.1/90540 https://orcid.org/0000-0001-9010-6519 |
| _version_ | 1826209362422530048 |
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| author | Postman, Jacob Krishna, Tushar Edmonds, Christopher Peh, Li-Shiuan Chiang, Patrick |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Postman, Jacob Krishna, Tushar Edmonds, Christopher Peh, Li-Shiuan Chiang, Patrick |
| author_sort | Postman, Jacob |
| collection | MIT |
| description | A 64-bit, 8 × 8 mesh network-on-chip (NoC) is presented that uses both new architectural and circuit design techniques to improve on-chip network energy-efficiency, latency, and throughput. First, we propose token flow control, which enables bypassing of flit buffering in routers, thereby reducing buffer size and their power consumption. We also incorporate reduced-swing signaling in on-chip links and crossbars to minimize datapath interconnect energy. The 64-node NoC is experimentally validated with a 2 × 2 test chip in 90 nm, 1.2 V CMOS that incorporates traffic generators to emulate the traffic of the full network. Compared with a fully synthesized baseline 8 × 8 NoC architecture designed to meet the same peak throughput, the fabricated prototype reduces network latency by 20% under uniform random traffic, when both networks are run at their maximum operating frequencies. When operated at the same frequencies, the SWIFT NoC reduces network power by 38% and 25% at saturation and low loads, respectively. |
| first_indexed | 2024-09-23T14:21:39Z |
| format | Article |
| id | mit-1721.1/90540 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T14:21:39Z |
| publishDate | 2014 |
| publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| record_format | dspace |
| spelling | mit-1721.1/905402022-09-29T08:55:31Z SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects Postman, Jacob Krishna, Tushar Edmonds, Christopher Peh, Li-Shiuan Chiang, Patrick Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Krishna, Tushar Peh, Li-Shiuan A 64-bit, 8 × 8 mesh network-on-chip (NoC) is presented that uses both new architectural and circuit design techniques to improve on-chip network energy-efficiency, latency, and throughput. First, we propose token flow control, which enables bypassing of flit buffering in routers, thereby reducing buffer size and their power consumption. We also incorporate reduced-swing signaling in on-chip links and crossbars to minimize datapath interconnect energy. The 64-node NoC is experimentally validated with a 2 × 2 test chip in 90 nm, 1.2 V CMOS that incorporates traffic generators to emulate the traffic of the full network. Compared with a fully synthesized baseline 8 × 8 NoC architecture designed to meet the same peak throughput, the fabricated prototype reduces network latency by 20% under uniform random traffic, when both networks are run at their maximum operating frequencies. When operated at the same frequencies, the SWIFT NoC reduces network power by 38% and 25% at saturation and low loads, respectively. 2014-10-02T16:51:10Z 2014-10-02T16:51:10Z 2013-08 Article http://purl.org/eprint/type/JournalArticle 1063-8210 1557-9999 http://hdl.handle.net/1721.1/90540 Postman, Jacob, Tushar Krishna, Christopher Edmonds, Li-Shiuan Peh, and Patrick Chiang. “SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, no. 8 (August 2013): 1432–1446. https://orcid.org/0000-0001-9010-6519 en_US http://dx.doi.org/10.1109/tvlsi.2012.2211904 IEEE Transactions on Very Large Scale Integration (VLSI) Systems Creative Commons Attribution-Noncommercial-Share Alike http://creativecommons.org/licenses/by-nc-sa/4.0/ application/pdf Institute of Electrical and Electronics Engineers (IEEE) MIT web domain |
| spellingShingle | Postman, Jacob Krishna, Tushar Edmonds, Christopher Peh, Li-Shiuan Chiang, Patrick SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects |
| title | SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects |
| title_full | SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects |
| title_fullStr | SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects |
| title_full_unstemmed | SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects |
| title_short | SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects |
| title_sort | swift a low power network on chip implementing the token flow control router architecture with swing reduced interconnects |
| url | http://hdl.handle.net/1721.1/90540 https://orcid.org/0000-0001-9010-6519 |
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