Reduced hardware transactions: a new approach to hybrid transactional memory
For many years, the accepted wisdom has been that the key to adoption of best-effort hardware transactions is to guarantee progress by combining them with an all software slow-path, to be taken if the hardware transactions fail repeatedly. However, all known generally applicable hybrid transactional...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Article |
| Language: | en_US |
| Published: |
Association for Computing Machinery (ACM)
2014
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| Online Access: | http://hdl.handle.net/1721.1/90886 https://orcid.org/0000-0002-4552-2414 |
| _version_ | 1826204661528395776 |
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| author | Matveev, Alexander Shavit, Nir N. |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Matveev, Alexander Shavit, Nir N. |
| author_sort | Matveev, Alexander |
| collection | MIT |
| description | For many years, the accepted wisdom has been that the key to adoption of best-effort hardware transactions is to guarantee progress by combining them with an all software slow-path, to be taken if the hardware transactions fail repeatedly. However, all known generally applicable hybrid transactional memory solutions suffer from a major drawback: the coordination with the software slow-path introduces an unacceptably high instrumentation overhead into the hardware transactions.
This paper overcomes the problem using a new approach which we call reduced hardware (RH) transactions. Instead of an all-software slow path, in RH transactions part of the slow-path is executed using a smaller hardware transaction. The purpose of this hardware component is not to speed up the slow-path (though this is a side effect). Rather, using it we are able to eliminate almost all of the instrumentation from the common hardware fast-path, making it virtually as fast as a pure hardware transaction. Moreover, the "mostly software" slow-path is obstruction-free (no locks), allows execution of long transactions and protected instructions that may typically cause hardware transactions to fail, allows complete concurrency between hardware and software transactions, and uses the shorter hardware transactions only to commit.
Finally, we show how to easily default to a mode allowing an all-software slow-slow mode in case the "mostly software" slow-path fails to commit. |
| first_indexed | 2024-09-23T12:58:59Z |
| format | Article |
| id | mit-1721.1/90886 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T12:58:59Z |
| publishDate | 2014 |
| publisher | Association for Computing Machinery (ACM) |
| record_format | dspace |
| spelling | mit-1721.1/908862022-09-28T11:17:37Z Reduced hardware transactions: a new approach to hybrid transactional memory Matveev, Alexander Shavit, Nir N. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Shavit, Nir N. For many years, the accepted wisdom has been that the key to adoption of best-effort hardware transactions is to guarantee progress by combining them with an all software slow-path, to be taken if the hardware transactions fail repeatedly. However, all known generally applicable hybrid transactional memory solutions suffer from a major drawback: the coordination with the software slow-path introduces an unacceptably high instrumentation overhead into the hardware transactions. This paper overcomes the problem using a new approach which we call reduced hardware (RH) transactions. Instead of an all-software slow path, in RH transactions part of the slow-path is executed using a smaller hardware transaction. The purpose of this hardware component is not to speed up the slow-path (though this is a side effect). Rather, using it we are able to eliminate almost all of the instrumentation from the common hardware fast-path, making it virtually as fast as a pure hardware transaction. Moreover, the "mostly software" slow-path is obstruction-free (no locks), allows execution of long transactions and protected instructions that may typically cause hardware transactions to fail, allows complete concurrency between hardware and software transactions, and uses the shorter hardware transactions only to commit. Finally, we show how to easily default to a mode allowing an all-software slow-slow mode in case the "mostly software" slow-path fails to commit. National Science Foundation (U.S.) (Grant CCF-1217921) United States. Dept. of Energy. Office of Advanced Scientific Computing Research (Grant ER26116/DE-SC0008923) Oracle Corporation Intel Corporation 2014-10-10T14:53:09Z 2014-10-10T14:53:09Z 2013-07 Article http://purl.org/eprint/type/ConferencePaper 9781450315722 http://hdl.handle.net/1721.1/90886 Alexander Matveev and Nir Shavit. 2013. Reduced hardware transactions: a new approach to hybrid transactional memory. In Proceedings of the twenty-fifth annual ACM symposium on Parallelism in algorithms and architectures (SPAA '13). ACM, New York, NY, USA, 11-22. https://orcid.org/0000-0002-4552-2414 en_US http://dx.doi.org/10.1145/2486159.2486188 Proceedings of the 25th ACM symposium on Parallelism in algorithms and architectures (SPAA '13) Creative Commons Attribution-Noncommercial-Share Alike http://creativecommons.org/licenses/by-nc-sa/4.0/ application/pdf Association for Computing Machinery (ACM) Other univ. web domain |
| spellingShingle | Matveev, Alexander Shavit, Nir N. Reduced hardware transactions: a new approach to hybrid transactional memory |
| title | Reduced hardware transactions: a new approach to hybrid transactional memory |
| title_full | Reduced hardware transactions: a new approach to hybrid transactional memory |
| title_fullStr | Reduced hardware transactions: a new approach to hybrid transactional memory |
| title_full_unstemmed | Reduced hardware transactions: a new approach to hybrid transactional memory |
| title_short | Reduced hardware transactions: a new approach to hybrid transactional memory |
| title_sort | reduced hardware transactions a new approach to hybrid transactional memory |
| url | http://hdl.handle.net/1721.1/90886 https://orcid.org/0000-0002-4552-2414 |
| work_keys_str_mv | AT matveevalexander reducedhardwaretransactionsanewapproachtohybridtransactionalmemory AT shavitnirn reducedhardwaretransactionsanewapproachtohybridtransactionalmemory |