Two-Layer Error Control Codes Combining Rectangular and Hamming Product Codes for Cache Error
We propose a novel two-layer error control code, combining error detection capability of rectangular codes and error correction capability of Hamming product codes in an efficient way, in order to increase cache error resilience for many core systems, while maintaining low power, area and latency ov...
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| Format: | Article |
| Language: | en_US |
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MDPI AG
2014
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| Online Access: | http://hdl.handle.net/1721.1/90921 |
| _version_ | 1826207389944119296 |
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| author | Zhang, Meilin Ampadu, Paul |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Zhang, Meilin Ampadu, Paul |
| author_sort | Zhang, Meilin |
| collection | MIT |
| description | We propose a novel two-layer error control code, combining error detection capability of rectangular codes and error correction capability of Hamming product codes in an efficient way, in order to increase cache error resilience for many core systems, while maintaining low power, area and latency overhead. Based on the fact of low latency and overhead of rectangular codes and high error control capability of Hamming product codes, two-layer error control codes employ simple rectangular codes for each cache line to detect cache errors, while loading the extra Hamming product code checks bits in the case of error detection; thus enabling reliable large-scale cache operations. Analysis and experiments are conducted to evaluate the cache fault-tolerant capability of various existing solutions and the proposed approach. The results show that the proposed approach can significantly increase Mean-Error-To-Failure (METF) and Mean-Time-To-failure (MTTF) up to 2.8×, reduce storage overhead by over 57%, and increase instruction per-cycle (IPC) up to 7%, compared to complex four-way 4EC5ED; and it increases METF and MTTF up to 133×, reduces storage overhead by over 11%, and achieves a similar IPC compared to simple eight-way single-error correcting double-error detecting (SECDED). The cost of the proposed approach is no more than 4% external memory access overhead. |
| first_indexed | 2024-09-23T13:48:33Z |
| format | Article |
| id | mit-1721.1/90921 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T13:48:33Z |
| publishDate | 2014 |
| publisher | MDPI AG |
| record_format | dspace |
| spelling | mit-1721.1/909212022-09-28T16:20:27Z Two-Layer Error Control Codes Combining Rectangular and Hamming Product Codes for Cache Error Zhang, Meilin Ampadu, Paul Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Ampadu, Paul We propose a novel two-layer error control code, combining error detection capability of rectangular codes and error correction capability of Hamming product codes in an efficient way, in order to increase cache error resilience for many core systems, while maintaining low power, area and latency overhead. Based on the fact of low latency and overhead of rectangular codes and high error control capability of Hamming product codes, two-layer error control codes employ simple rectangular codes for each cache line to detect cache errors, while loading the extra Hamming product code checks bits in the case of error detection; thus enabling reliable large-scale cache operations. Analysis and experiments are conducted to evaluate the cache fault-tolerant capability of various existing solutions and the proposed approach. The results show that the proposed approach can significantly increase Mean-Error-To-Failure (METF) and Mean-Time-To-failure (MTTF) up to 2.8×, reduce storage overhead by over 57%, and increase instruction per-cycle (IPC) up to 7%, compared to complex four-way 4EC5ED; and it increases METF and MTTF up to 133×, reduces storage overhead by over 11%, and achieves a similar IPC compared to simple eight-way single-error correcting double-error detecting (SECDED). The cost of the proposed approach is no more than 4% external memory access overhead. 2014-10-14T19:53:09Z 2014-10-14T19:53:09Z 2014-02 2014-01 Article http://purl.org/eprint/type/JournalArticle 2079-9268 http://hdl.handle.net/1721.1/90921 Zhang, Meilin, and Paul Ampadu. “Two-Layer Error Control Codes Combining Rectangular and Hamming Product Codes for Cache Error.” Journal of Low Power Electronics and Applications 4, no. 1 (February 27, 2014): 44–62. en_US http://dx.doi.org/10.3390/jlpea4010044 Journal of Low Power Electronics and Applications Creative Commons Attribution http://creativecommons.org/licenses/by/3.0/ application/pdf MDPI AG MDPI Publishing |
| spellingShingle | Zhang, Meilin Ampadu, Paul Two-Layer Error Control Codes Combining Rectangular and Hamming Product Codes for Cache Error |
| title | Two-Layer Error Control Codes Combining Rectangular and Hamming Product Codes for Cache Error |
| title_full | Two-Layer Error Control Codes Combining Rectangular and Hamming Product Codes for Cache Error |
| title_fullStr | Two-Layer Error Control Codes Combining Rectangular and Hamming Product Codes for Cache Error |
| title_full_unstemmed | Two-Layer Error Control Codes Combining Rectangular and Hamming Product Codes for Cache Error |
| title_short | Two-Layer Error Control Codes Combining Rectangular and Hamming Product Codes for Cache Error |
| title_sort | two layer error control codes combining rectangular and hamming product codes for cache error |
| url | http://hdl.handle.net/1721.1/90921 |
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