An on-chip input driver for a high-voltage SAR ADC

Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.

Bibliographic Details
Main Author: Linke, Kevin Robert
Other Authors: Micah G. O'Halloran and Charles G. Sodini.
Format: Thesis
Language:eng
Published: Massachusetts Institute of Technology 2014
Subjects:
Online Access:http://hdl.handle.net/1721.1/91837
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author Linke, Kevin Robert
author2 Micah G. O'Halloran and Charles G. Sodini.
author_facet Micah G. O'Halloran and Charles G. Sodini.
Linke, Kevin Robert
author_sort Linke, Kevin Robert
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spelling mit-1721.1/918372019-04-10T23:21:46Z An on-chip input driver for a high-voltage SAR ADC Linke, Kevin Robert Micah G. O'Halloran and Charles G. Sodini. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014. Cataloged from PDF version of thesis. Includes bibliographical references (page 49). This thesis describes the design of a novel on-chip input driver for a SAR ADC. The driver achieves performance gains relative to off-chip alternatives by being integrated into the signal path of the ADC between the sampling switches and sampling capacitor. This placement allows for auto-zeroing the offset of the driver and reducing flicker noise. Additional performance benefits are possible because the driver can be optimized for the specific load and timings of the ADC. The most important benefit of an on-chip input driver is that it simplifies the design process for the ADC user by eliminating the external op-amp and reducing the constraints on the external filter by reducing input current load. Design simplicity is especially important to users in high-voltage SAR ADC applications, so the input driver is designed for an ADC with a +/- 10.24 V input range and +/- 15 V supply rails. This high-voltage input relaxes noise and headroom constraints, but makes device overvoltage a significant concern. The driver is designed in a BiCMOS process, and simulation results with a computer-modeled ADC are presented here. In these simulations, the driver achieves a THD of -124.7 dB at 2 kHz and a noise voltage spectral density of 5.5 nV / [square root of] Hz with a power consumption of 27.6 mW. The LT1469, an example of a state-of-the-art external input driver, has a THD of -123 dB at 2 kHz, a noise voltage spectral density of 5 nV / [square root of] Hz, and a power consumption of 123 mW. by Kevin Robert Linke. M. Eng. 2014-11-24T18:38:47Z 2014-11-24T18:38:47Z 2014 2014 Thesis http://hdl.handle.net/1721.1/91837 894241316 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 49 pages application/pdf Massachusetts Institute of Technology
spellingShingle Electrical Engineering and Computer Science.
Linke, Kevin Robert
An on-chip input driver for a high-voltage SAR ADC
title An on-chip input driver for a high-voltage SAR ADC
title_full An on-chip input driver for a high-voltage SAR ADC
title_fullStr An on-chip input driver for a high-voltage SAR ADC
title_full_unstemmed An on-chip input driver for a high-voltage SAR ADC
title_short An on-chip input driver for a high-voltage SAR ADC
title_sort on chip input driver for a high voltage sar adc
topic Electrical Engineering and Computer Science.
url http://hdl.handle.net/1721.1/91837
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