Building blocks of a 250MHz bandwidth, 10-bit continuous-time delta-sigma analog to digital converter
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2014
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| Online Access: | http://hdl.handle.net/1721.1/91886 |
| _version_ | 1811098004301545472 |
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| author2 | Charles G. Sodini and Benjamin Walker. |
| author_facet | Charles G. Sodini and Benjamin Walker. |
| collection | MIT |
| description | Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014. |
| first_indexed | 2024-09-23T17:08:26Z |
| format | Thesis |
| id | mit-1721.1/91886 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T17:08:26Z |
| publishDate | 2014 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/918862019-04-11T13:57:37Z Building blocks of a 250MHz bandwidth, 10-bit continuous-time delta-sigma analog to digital converter Design blocks of a continuous-time delta-sigma ADC in a BiCMOS technology Charles G. Sodini and Benjamin Walker. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014. Cataloged from PDF version of thesis. Includes bibliographical references (pages 93-94). This thesis examines the design of a continuous time Delta-Sigma Analog to Digital Converter with the target performance to be 10-bit, 250MHz bandwidth with 200mW power dissipation.The design process involves choosing a top-level architecture and designing transistor-level blocks. The architecture is selected to be second-order, 3-bit with a 32 oversampling rate based on the ideal model simulation in MATLAB. The transistor-level circuits are designed in a BiCMOS technology. The SQNR result is 63.3dB and the power is 140mW. by Xianzhen Zhu. M. Eng. 2014-11-24T18:42:39Z 2014-11-24T18:42:39Z 2014 2014 Thesis http://hdl.handle.net/1721.1/91886 894502748 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 94 pages application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Building blocks of a 250MHz bandwidth, 10-bit continuous-time delta-sigma analog to digital converter |
| title | Building blocks of a 250MHz bandwidth, 10-bit continuous-time delta-sigma analog to digital converter |
| title_full | Building blocks of a 250MHz bandwidth, 10-bit continuous-time delta-sigma analog to digital converter |
| title_fullStr | Building blocks of a 250MHz bandwidth, 10-bit continuous-time delta-sigma analog to digital converter |
| title_full_unstemmed | Building blocks of a 250MHz bandwidth, 10-bit continuous-time delta-sigma analog to digital converter |
| title_short | Building blocks of a 250MHz bandwidth, 10-bit continuous-time delta-sigma analog to digital converter |
| title_sort | building blocks of a 250mhz bandwidth 10 bit continuous time delta sigma analog to digital converter |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/91886 |