Methodology for analysis of TSV stress induced transistor variation and circuit performance
As continued scaling becomes increasingly difficult, 3D integration with through silicon vias (TSVs) has emerged as a viable solution to achieve higher bandwidth and power efficiency. Mechanical stress induced by thermal mismatch between TSVs and the silicon bulk arising during wafer fabrication and...
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| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers (IEEE)
2014
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| Online Access: | http://hdl.handle.net/1721.1/92361 https://orcid.org/0000-0002-0417-445X |
| _version_ | 1826189126990299136 |
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| author | Yu, Li Chang, Wen-Yao Zuo, Kewei Wang, Jean Yu, Douglas Boning, Duane S. |
| author2 | Massachusetts Institute of Technology. Microsystems Technology Laboratories |
| author_facet | Massachusetts Institute of Technology. Microsystems Technology Laboratories Yu, Li Chang, Wen-Yao Zuo, Kewei Wang, Jean Yu, Douglas Boning, Duane S. |
| author_sort | Yu, Li |
| collection | MIT |
| description | As continued scaling becomes increasingly difficult, 3D integration with through silicon vias (TSVs) has emerged as a viable solution to achieve higher bandwidth and power efficiency. Mechanical stress induced by thermal mismatch between TSVs and the silicon bulk arising during wafer fabrication and 3D integration, is a key constraint. In this work, we propose a complete flow to characterize the influence of TSV stress on transistor and circuit performance. First, we analyze the thermal stress contour near the silicon surface with single and multiple TSVs through both finite element analysis (FEA) and linear superposition methods. Then, the biaxial stress is converted to mobility and threshold voltage variations depending on transistor type and geometric relation between TSVs and transistors. Next, we propose an efficient algorithm to calculate circuit variation corresponding to TSV stress based on a grid partition approach. Finally, we discuss a TSV pattern optimization strategy, and employ a series of 17-stage ring oscillators using 40 nm CMOS technology as a test case for the proposed approach. |
| first_indexed | 2024-09-23T08:10:16Z |
| format | Article |
| id | mit-1721.1/92361 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T08:10:16Z |
| publishDate | 2014 |
| publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| record_format | dspace |
| spelling | mit-1721.1/923612022-09-30T08:02:20Z Methodology for analysis of TSV stress induced transistor variation and circuit performance Yu, Li Chang, Wen-Yao Zuo, Kewei Wang, Jean Yu, Douglas Boning, Duane S. Massachusetts Institute of Technology. Microsystems Technology Laboratories Boning, Duane S. Yu, Li Boning, Duane S. As continued scaling becomes increasingly difficult, 3D integration with through silicon vias (TSVs) has emerged as a viable solution to achieve higher bandwidth and power efficiency. Mechanical stress induced by thermal mismatch between TSVs and the silicon bulk arising during wafer fabrication and 3D integration, is a key constraint. In this work, we propose a complete flow to characterize the influence of TSV stress on transistor and circuit performance. First, we analyze the thermal stress contour near the silicon surface with single and multiple TSVs through both finite element analysis (FEA) and linear superposition methods. Then, the biaxial stress is converted to mobility and threshold voltage variations depending on transistor type and geometric relation between TSVs and transistors. Next, we propose an efficient algorithm to calculate circuit variation corresponding to TSV stress based on a grid partition approach. Finally, we discuss a TSV pattern optimization strategy, and employ a series of 17-stage ring oscillators using 40 nm CMOS technology as a test case for the proposed approach. 2014-12-17T21:37:17Z 2014-12-17T21:37:17Z 2012-03 Article http://purl.org/eprint/type/ConferencePaper 978-1-4673-1036-9 978-1-4673-1034-5 978-1-4673-1035-2 1948-3287 INSPEC Accession Number:12691839 http://hdl.handle.net/1721.1/92361 Yu, Li, Wen-Yao Chang, Kewei Zuo, Jean Wang, Douglas Yu, and Duane Boning. “Methodology for Analysis of TSV Stress Induced Transistor Variation and Circuit Performance.” Thirteenth International Symposium on Quality Electronic Design (ISQED) (March 19-21, 2012), Santa Clara, California. IEEE. p.216-222. https://orcid.org/0000-0002-0417-445X en_US http://dx.doi.org/10.1109/ISQED.2012.6187497 Proceedings of the 2012 Thirteenth International Symposium on Quality Electronic Design (ISQED) Creative Commons Attribution-Noncommercial-Share Alike http://creativecommons.org/licenses/by-nc-sa/4.0/ application/pdf Institute of Electrical and Electronics Engineers (IEEE) Boning |
| spellingShingle | Yu, Li Chang, Wen-Yao Zuo, Kewei Wang, Jean Yu, Douglas Boning, Duane S. Methodology for analysis of TSV stress induced transistor variation and circuit performance |
| title | Methodology for analysis of TSV stress induced transistor variation and circuit performance |
| title_full | Methodology for analysis of TSV stress induced transistor variation and circuit performance |
| title_fullStr | Methodology for analysis of TSV stress induced transistor variation and circuit performance |
| title_full_unstemmed | Methodology for analysis of TSV stress induced transistor variation and circuit performance |
| title_short | Methodology for analysis of TSV stress induced transistor variation and circuit performance |
| title_sort | methodology for analysis of tsv stress induced transistor variation and circuit performance |
| url | http://hdl.handle.net/1721.1/92361 https://orcid.org/0000-0002-0417-445X |
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