A Deeply Pipelined CABAC Decoder for HEVC Supporting Level 6.2 High-tier Applications
High Efficiency Video Coding (HEVC) is the latest video coding standard that specifies video resolutions up to 8K Ultra-HD (UHD) at 120 fps to support the next decade of video applications. This results in high-throughput requirements for the context adaptive binary arithmetic coding (CABAC) entropy...
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| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers (IEEE)
2015
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| Online Access: | http://hdl.handle.net/1721.1/92837 https://orcid.org/0000-0002-4403-956X https://orcid.org/0000-0003-4841-3990 |
| _version_ | 1826206473024176128 |
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| author | Chen, Yu-Hsin Sze, Vivienne |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Chen, Yu-Hsin Sze, Vivienne |
| author_sort | Chen, Yu-Hsin |
| collection | MIT |
| description | High Efficiency Video Coding (HEVC) is the latest video coding standard that specifies video resolutions up to 8K Ultra-HD (UHD) at 120 fps to support the next decade of video applications. This results in high-throughput requirements for the context adaptive binary arithmetic coding (CABAC) entropy decoder, which was already a well-known bottleneck in H.264/AVC. To address the throughput challenges, several modifications were made to CABAC during the standardization of HEVC. This work leverages these improvements in the design of a high-throughput HEVC CABAC decoder. It also supports the high-level parallel processing tools introduced by HEVC, including tile and wavefront parallel processing. The proposed design uses a deeply pipelined architecture to achieve a high clock rate. Additional techniques such as the state prefetch logic, latched-based context memory, and separate finite state machines are applied to minimize stall cycles, while multibypass- bin decoding is used to further increase the throughput. The design is implemented in an IBM 45nm SOI process. After place-and-route, its operating frequency reaches 1.6 GHz. The corresponding throughputs achieve up to 1696 and 2314 Mbin/s under common and theoretical worst-case test conditions, respectively. The results show that the design is sufficient to decode in real-time high-tier video bitstreams at level 6.2 (8K UHD at 120 fps), or main-tier bitstreams at level 5.1 (4K UHD at 60 fps) for applications requiring sub-frame latency, such as video conferencing. |
| first_indexed | 2024-09-23T13:32:12Z |
| format | Article |
| id | mit-1721.1/92837 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T13:32:12Z |
| publishDate | 2015 |
| publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| record_format | dspace |
| spelling | mit-1721.1/928372022-10-01T15:38:08Z A Deeply Pipelined CABAC Decoder for HEVC Supporting Level 6.2 High-tier Applications Chen, Yu-Hsin Sze, Vivienne Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Sze, Vivienne Chen, Yu-Hsin Sze, Vivienne High Efficiency Video Coding (HEVC) is the latest video coding standard that specifies video resolutions up to 8K Ultra-HD (UHD) at 120 fps to support the next decade of video applications. This results in high-throughput requirements for the context adaptive binary arithmetic coding (CABAC) entropy decoder, which was already a well-known bottleneck in H.264/AVC. To address the throughput challenges, several modifications were made to CABAC during the standardization of HEVC. This work leverages these improvements in the design of a high-throughput HEVC CABAC decoder. It also supports the high-level parallel processing tools introduced by HEVC, including tile and wavefront parallel processing. The proposed design uses a deeply pipelined architecture to achieve a high clock rate. Additional techniques such as the state prefetch logic, latched-based context memory, and separate finite state machines are applied to minimize stall cycles, while multibypass- bin decoding is used to further increase the throughput. The design is implemented in an IBM 45nm SOI process. After place-and-route, its operating frequency reaches 1.6 GHz. The corresponding throughputs achieve up to 1696 and 2314 Mbin/s under common and theoretical worst-case test conditions, respectively. The results show that the design is sufficient to decode in real-time high-tier video bitstreams at level 6.2 (8K UHD at 120 fps), or main-tier bitstreams at level 5.1 (4K UHD at 60 fps) for applications requiring sub-frame latency, such as video conferencing. 2015-01-13T20:39:33Z 2015-01-13T20:39:33Z 2014-10 Article http://purl.org/eprint/type/JournalArticle 1051-8215 1558-2205 http://hdl.handle.net/1721.1/92837 Chen, Yu-Hsin, and Vivienne Sze. “A Deeply Pipelined CABAC Decoder for HEVC Supporting Level 6.2 High-Tier Applications.” IEEE Trans. Circuits Syst. Video Technol. (2014): 1–1. https://orcid.org/0000-0002-4403-956X https://orcid.org/0000-0003-4841-3990 en_US http://dx.doi.org/10.1109/TCSVT.2014.2363748 IEEE Transactions on Circuits and Systems for Video Technology Creative Commons Attribution-Noncommercial-Share Alike http://creativecommons.org/licenses/by-nc-sa/4.0/ application/pdf Institute of Electrical and Electronics Engineers (IEEE) Sze |
| spellingShingle | Chen, Yu-Hsin Sze, Vivienne A Deeply Pipelined CABAC Decoder for HEVC Supporting Level 6.2 High-tier Applications |
| title | A Deeply Pipelined CABAC Decoder for HEVC Supporting Level 6.2 High-tier Applications |
| title_full | A Deeply Pipelined CABAC Decoder for HEVC Supporting Level 6.2 High-tier Applications |
| title_fullStr | A Deeply Pipelined CABAC Decoder for HEVC Supporting Level 6.2 High-tier Applications |
| title_full_unstemmed | A Deeply Pipelined CABAC Decoder for HEVC Supporting Level 6.2 High-tier Applications |
| title_short | A Deeply Pipelined CABAC Decoder for HEVC Supporting Level 6.2 High-tier Applications |
| title_sort | deeply pipelined cabac decoder for hevc supporting level 6 2 high tier applications |
| url | http://hdl.handle.net/1721.1/92837 https://orcid.org/0000-0002-4403-956X https://orcid.org/0000-0003-4841-3990 |
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