A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems
Nonvolatile processing-continuously operating a digital circuit and retaining state through frequent power interruptions-creates new applications for portable electronics operating from harvested energy and high-performance systems managing power by operating “normally off”. To enable these scenario...
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| Other Authors: | |
| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers (IEEE)
2015
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| Online Access: | http://hdl.handle.net/1721.1/93232 https://orcid.org/0000-0002-5977-2748 |
| _version_ | 1826203391721734144 |
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| author | Qazi, Masood Chandrakasan, Anantha P. Amerasekera, Ajith |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Qazi, Masood Chandrakasan, Anantha P. Amerasekera, Ajith |
| author_sort | Qazi, Masood |
| collection | MIT |
| description | Nonvolatile processing-continuously operating a digital circuit and retaining state through frequent power interruptions-creates new applications for portable electronics operating from harvested energy and high-performance systems managing power by operating “normally off”. To enable these scenarios, energy processing must happen in parallel with information processing. This work makes the following contributions: 1) the design of a nonvolatile D flip-flop (NVDFF) with embedded ferroelectric capacitors (fecaps) that senses data robustly and avoids race conditions; 2) the integration of the NVDFF into the ASIC design flow with a power management unit (PMU) and a simple one-bit interface to brown-out detection circuitry; and 3) a characterization of the NVDFF statistical signal margin and the energy cost of retaining data. |
| first_indexed | 2024-09-23T12:36:10Z |
| format | Article |
| id | mit-1721.1/93232 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T12:36:10Z |
| publishDate | 2015 |
| publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| record_format | dspace |
| spelling | mit-1721.1/932322022-09-28T08:55:09Z A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems Qazi, Masood Chandrakasan, Anantha P. Amerasekera, Ajith Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Chandrakasan, Anantha P. Qazi, Masood Chandrakasan, Anantha P. Nonvolatile processing-continuously operating a digital circuit and retaining state through frequent power interruptions-creates new applications for portable electronics operating from harvested energy and high-performance systems managing power by operating “normally off”. To enable these scenarios, energy processing must happen in parallel with information processing. This work makes the following contributions: 1) the design of a nonvolatile D flip-flop (NVDFF) with embedded ferroelectric capacitors (fecaps) that senses data robustly and avoids race conditions; 2) the integration of the NVDFF into the ASIC design flow with a power management unit (PMU) and a simple one-bit interface to brown-out detection circuitry; and 3) a characterization of the NVDFF statistical signal margin and the energy cost of retaining data. Focus Center Research Program. Focus Center for Circuit & System Solutions 2015-01-30T18:16:42Z 2015-01-30T18:16:42Z 2013-02 Article http://purl.org/eprint/type/ConferencePaper 978-1-4673-4516-3 978-1-4673-4515-6 978-1-4673-4514-9 0193-6530 http://hdl.handle.net/1721.1/93232 Qazi, M., A. Amerasekera, and A. P. Chandrakasan. “A 3.4pJ FeRAM-Enabled D Flip-Flop in 0.13µm CMOS for Nonvolatile Processing in Digital Systems.” 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (February 2013). https://orcid.org/0000-0002-5977-2748 en_US http://dx.doi.org/10.1109/ISSCC.2013.6487695 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Creative Commons Attribution-Noncommercial-Share Alike http://creativecommons.org/licenses/by-nc-sa/4.0/ application/pdf Institute of Electrical and Electronics Engineers (IEEE) Chandrakasan |
| spellingShingle | Qazi, Masood Chandrakasan, Anantha P. Amerasekera, Ajith A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems |
| title | A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems |
| title_full | A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems |
| title_fullStr | A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems |
| title_full_unstemmed | A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems |
| title_short | A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems |
| title_sort | 3 4pj feram enabled d flip flop in 0 13µm cmos for nonvolatile processing in digital systems |
| url | http://hdl.handle.net/1721.1/93232 https://orcid.org/0000-0002-5977-2748 |
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