Cost and Coding Efficient Motion Estimation Design Considerations for High Efficiency Video Coding (HEVC) Standard
This paper focuses on motion estimation engine design in future high-efficiency video coding (HEVC) encoders. First, a methodology is explained to analyze hardware implementation cost in terms of hardware area, memory size and memory bandwidth for various possible motion estimation engine designs. F...
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| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers (IEEE)
2015
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| Online Access: | http://hdl.handle.net/1721.1/95886 https://orcid.org/0000-0002-5977-2748 https://orcid.org/0000-0003-4841-3990 |
| _version_ | 1811079417099714560 |
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| author | Sze, Vivienne Chandrakasan, Anantha P. Sinangil, M. E. Zhou, M. |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Sze, Vivienne Chandrakasan, Anantha P. Sinangil, M. E. Zhou, M. |
| author_sort | Sze, Vivienne |
| collection | MIT |
| description | This paper focuses on motion estimation engine design in future high-efficiency video coding (HEVC) encoders. First, a methodology is explained to analyze hardware implementation cost in terms of hardware area, memory size and memory bandwidth for various possible motion estimation engine designs. For 11 different configurations, hardware cost as well as the coding efficiency are quantified and are compared through a graphical analysis to make design decisions. It has been shown that using smaller block sizes (e.g. 4 × 4) imposes significantly larger hardware requirements at the expense of modest improvements in coding efficiency. Secondly, based on the analysis on various configurations, one configuration is chosen and algorithm improvements are presented to further reduce hardware implementation cost of the selected configuration. Overall, the proposed changes provide 56 × on-chip bandwidth, 151 × off-chip bandwidth, 4.3 × core area and 4.5 × on-chip memory area savings when compared to the hardware implementation of the HM-3.0 design. |
| first_indexed | 2024-09-23T11:14:41Z |
| format | Article |
| id | mit-1721.1/95886 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T11:14:41Z |
| publishDate | 2015 |
| publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| record_format | dspace |
| spelling | mit-1721.1/958862022-10-01T02:18:01Z Cost and Coding Efficient Motion Estimation Design Considerations for High Efficiency Video Coding (HEVC) Standard Sze, Vivienne Chandrakasan, Anantha P. Sinangil, M. E. Zhou, M. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Chandrakasan, Anantha P. Sze, Vivienne Chandrakasan, Anantha P. This paper focuses on motion estimation engine design in future high-efficiency video coding (HEVC) encoders. First, a methodology is explained to analyze hardware implementation cost in terms of hardware area, memory size and memory bandwidth for various possible motion estimation engine designs. For 11 different configurations, hardware cost as well as the coding efficiency are quantified and are compared through a graphical analysis to make design decisions. It has been shown that using smaller block sizes (e.g. 4 × 4) imposes significantly larger hardware requirements at the expense of modest improvements in coding efficiency. Secondly, based on the analysis on various configurations, one configuration is chosen and algorithm improvements are presented to further reduce hardware implementation cost of the selected configuration. Overall, the proposed changes provide 56 × on-chip bandwidth, 151 × off-chip bandwidth, 4.3 × core area and 4.5 × on-chip memory area savings when compared to the hardware implementation of the HM-3.0 design. Texas Instruments Incorporated 2015-03-05T19:28:50Z 2015-03-05T19:28:50Z 2013-07 2013-05 Article http://purl.org/eprint/type/JournalArticle 1932-4553 1941-0484 http://hdl.handle.net/1721.1/95886 Sinangil, Mahmut E., Vivienne Sze, Minhua Zhou, and Anantha P. Chandrakasan. “Cost and Coding Efficient Motion Estimation Design Considerations for High Efficiency Video Coding (HEVC) Standard.” IEEE J. Sel. Top. Signal Process. 7, no. 6 (December 2013): 1017–1028. https://orcid.org/0000-0002-5977-2748 https://orcid.org/0000-0003-4841-3990 en_US http://dx.doi.org/10.1109/jstsp.2013.2273658 IEEE Journal of Selected Topics in Signal Processing Creative Commons Attribution-Noncommercial-Share Alike http://creativecommons.org/licenses/by-nc-sa/4.0/ application/pdf Institute of Electrical and Electronics Engineers (IEEE) Chandrakasan |
| spellingShingle | Sze, Vivienne Chandrakasan, Anantha P. Sinangil, M. E. Zhou, M. Cost and Coding Efficient Motion Estimation Design Considerations for High Efficiency Video Coding (HEVC) Standard |
| title | Cost and Coding Efficient Motion Estimation Design Considerations for High Efficiency Video Coding (HEVC) Standard |
| title_full | Cost and Coding Efficient Motion Estimation Design Considerations for High Efficiency Video Coding (HEVC) Standard |
| title_fullStr | Cost and Coding Efficient Motion Estimation Design Considerations for High Efficiency Video Coding (HEVC) Standard |
| title_full_unstemmed | Cost and Coding Efficient Motion Estimation Design Considerations for High Efficiency Video Coding (HEVC) Standard |
| title_short | Cost and Coding Efficient Motion Estimation Design Considerations for High Efficiency Video Coding (HEVC) Standard |
| title_sort | cost and coding efficient motion estimation design considerations for high efficiency video coding hevc standard |
| url | http://hdl.handle.net/1721.1/95886 https://orcid.org/0000-0002-5977-2748 https://orcid.org/0000-0003-4841-3990 |
| work_keys_str_mv | AT szevivienne costandcodingefficientmotionestimationdesignconsiderationsforhighefficiencyvideocodinghevcstandard AT chandrakasanananthap costandcodingefficientmotionestimationdesignconsiderationsforhighefficiencyvideocodinghevcstandard AT sinangilme costandcodingefficientmotionestimationdesignconsiderationsforhighefficiencyvideocodinghevcstandard AT zhoum costandcodingefficientmotionestimationdesignconsiderationsforhighefficiencyvideocodinghevcstandard |