Memory cost vs. coding efficiency trade-offs for HEVC motion estimation engine
This paper presents a comparison between various High Efficiency Video Coding (HEVC) motion estimation configurations in terms of coding efficiency and memory cost in hardware. An HEVC motion estimation hardware model that is suitable to implement HEVC reference software (HM) search algorithm is cre...
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| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers (IEEE)
2015
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| Online Access: | http://hdl.handle.net/1721.1/95887 https://orcid.org/0000-0002-5977-2748 https://orcid.org/0000-0003-4841-3990 |
| _version_ | 1811084882653216768 |
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| author | Sinangil, Mahmut E. Chandrakasan, Anantha P. Sze, Vivienne Zhou, Minhua Sinangil, Mahmut |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Sinangil, Mahmut E. Chandrakasan, Anantha P. Sze, Vivienne Zhou, Minhua Sinangil, Mahmut |
| author_sort | Sinangil, Mahmut E. |
| collection | MIT |
| description | This paper presents a comparison between various High Efficiency Video Coding (HEVC) motion estimation configurations in terms of coding efficiency and memory cost in hardware. An HEVC motion estimation hardware model that is suitable to implement HEVC reference software (HM) search algorithm is created and memory area and data bandwidth requirements are calculated based on this model. 11 different motion estimation configurations are considered. Supporting smaller block sizes is shown to impose significant memory cost in hardware although the coding gain achieved through supporting them is relatively smaller. Hence, depending on target encoder specifications, the decision can be made not to support certain block sizes. Specifically, supporting only 64x64, 32x32 and 16x16 block sizes provide 3.2X on-chip memory area, 26X on-chip bandwidth and 12.5X off-chip bandwidth savings at the expense of 12% bit-rate increase when compared to the anchor configuration supporting all block sizes. |
| first_indexed | 2024-09-23T12:59:00Z |
| format | Article |
| id | mit-1721.1/95887 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T12:59:00Z |
| publishDate | 2015 |
| publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| record_format | dspace |
| spelling | mit-1721.1/958872022-10-01T12:19:40Z Memory cost vs. coding efficiency trade-offs for HEVC motion estimation engine Sinangil, Mahmut E. Chandrakasan, Anantha P. Sze, Vivienne Zhou, Minhua Sinangil, Mahmut Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Chandrakasan, Anantha P. Sinangil, Mahmut Chandrakasan, Anantha P. Sze, Vivienne This paper presents a comparison between various High Efficiency Video Coding (HEVC) motion estimation configurations in terms of coding efficiency and memory cost in hardware. An HEVC motion estimation hardware model that is suitable to implement HEVC reference software (HM) search algorithm is created and memory area and data bandwidth requirements are calculated based on this model. 11 different motion estimation configurations are considered. Supporting smaller block sizes is shown to impose significant memory cost in hardware although the coding gain achieved through supporting them is relatively smaller. Hence, depending on target encoder specifications, the decision can be made not to support certain block sizes. Specifically, supporting only 64x64, 32x32 and 16x16 block sizes provide 3.2X on-chip memory area, 26X on-chip bandwidth and 12.5X off-chip bandwidth savings at the expense of 12% bit-rate increase when compared to the anchor configuration supporting all block sizes. Texas Instruments Incorporated 2015-03-05T19:37:27Z 2015-03-05T19:37:27Z 2012-09 Article http://purl.org/eprint/type/ConferencePaper 978-1-4673-2533-2 978-1-4673-2534-9 978-1-4673-2532-5 1522-4880 http://hdl.handle.net/1721.1/95887 Sinangil, Mahmut E., Anantha P. Chandrakasan, Vivienne Sze, and Minhua Zhou. “Memory Cost Vs. Coding Efficiency Trade-Offs for HEVC Motion Estimation Engine.” 2012 19th IEEE International Conference on Image Processing (September 2012). https://orcid.org/0000-0002-5977-2748 https://orcid.org/0000-0003-4841-3990 en_US http://dx.doi.org/10.1109/ICIP.2012.6467164 Proceedings of the 2012 19th IEEE International Conference on Image Processing (ICIP) Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. application/pdf Institute of Electrical and Electronics Engineers (IEEE) Chandrakasan |
| spellingShingle | Sinangil, Mahmut E. Chandrakasan, Anantha P. Sze, Vivienne Zhou, Minhua Sinangil, Mahmut Memory cost vs. coding efficiency trade-offs for HEVC motion estimation engine |
| title | Memory cost vs. coding efficiency trade-offs for HEVC motion estimation engine |
| title_full | Memory cost vs. coding efficiency trade-offs for HEVC motion estimation engine |
| title_fullStr | Memory cost vs. coding efficiency trade-offs for HEVC motion estimation engine |
| title_full_unstemmed | Memory cost vs. coding efficiency trade-offs for HEVC motion estimation engine |
| title_short | Memory cost vs. coding efficiency trade-offs for HEVC motion estimation engine |
| title_sort | memory cost vs coding efficiency trade offs for hevc motion estimation engine |
| url | http://hdl.handle.net/1721.1/95887 https://orcid.org/0000-0002-5977-2748 https://orcid.org/0000-0003-4841-3990 |
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