Analysis and Design of Regular Structures for Robust Dynamic Fault Testability
Recent methods of synthesizing logic that is fully and robustly testable for dynamic faults, namely path delay, transistor stuck-open and gate delay faults, rely almost exclusively on flattening given logic expressions into sum-of-products form, minimizing the cover to obtain a fully dynamic-fault t...
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| Format: | Article |
| Language: | English |
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Hindawi Publishing Corporation
2015
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| Online Access: | http://hdl.handle.net/1721.1/96136 https://orcid.org/0000-0001-8253-7714 |
| _version_ | 1826201351280918528 |
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| author | Bryan, Michael J. Devadas, Srinivas Keutzer, Kurt |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Bryan, Michael J. Devadas, Srinivas Keutzer, Kurt |
| author_sort | Bryan, Michael J. |
| collection | MIT |
| description | Recent methods of synthesizing logic that is fully and robustly testable for dynamic faults, namely path delay, transistor stuck-open and gate delay faults, rely almost exclusively on flattening given logic expressions into sum-of-products form, minimizing the cover to obtain a fully dynamic-fault testable two-level representation of the functions, and performing structural transformations to resynthesize the circuit into a multilevel network, while also maintaining full dynamic-fault testability. While this technique will work well for random or control logic, it is not practical for many regular structures.To deal with the synthesis of regular structures for dynamic-fault testability, we present a method that involves the development of a library of cells for these regular structures such that the cells are all fully path-delay-fault, transistor stuck-open fault or gate-delay-fault testable. These cells can then be utilized whenever one of these standard functions is encountered.We analyze various regular structures such as adders, arithmetic logic units, comparators, multipliers, and parity generators to determine if they are testable for dynamic faults, or how they can be modified to be testable for dynamic faults while still maintaining good area and performance characteristics. In addition to minimizing the area and delay, another key consideration is to get designs which can be scaled to an arbitrary number of bits while still maintaining complete testability. In each case, the emphasis is on obtaining circuits which are fully path-delay-fault testable. In the process of design modification to produce fully robustly testable structures, we have derived a number of new composition rules that allow cascading individual modules while maintaining robust
testability under dynamic fault models. |
| first_indexed | 2024-09-23T11:50:34Z |
| format | Article |
| id | mit-1721.1/96136 |
| institution | Massachusetts Institute of Technology |
| language | English |
| last_indexed | 2024-09-23T11:50:34Z |
| publishDate | 2015 |
| publisher | Hindawi Publishing Corporation |
| record_format | dspace |
| spelling | mit-1721.1/961362022-10-01T06:21:33Z Analysis and Design of Regular Structures for Robust Dynamic Fault Testability Bryan, Michael J. Devadas, Srinivas Keutzer, Kurt Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Bryan, Michael J. Devadas, Srinivas Recent methods of synthesizing logic that is fully and robustly testable for dynamic faults, namely path delay, transistor stuck-open and gate delay faults, rely almost exclusively on flattening given logic expressions into sum-of-products form, minimizing the cover to obtain a fully dynamic-fault testable two-level representation of the functions, and performing structural transformations to resynthesize the circuit into a multilevel network, while also maintaining full dynamic-fault testability. While this technique will work well for random or control logic, it is not practical for many regular structures.To deal with the synthesis of regular structures for dynamic-fault testability, we present a method that involves the development of a library of cells for these regular structures such that the cells are all fully path-delay-fault, transistor stuck-open fault or gate-delay-fault testable. These cells can then be utilized whenever one of these standard functions is encountered.We analyze various regular structures such as adders, arithmetic logic units, comparators, multipliers, and parity generators to determine if they are testable for dynamic faults, or how they can be modified to be testable for dynamic faults while still maintaining good area and performance characteristics. In addition to minimizing the area and delay, another key consideration is to get designs which can be scaled to an arbitrary number of bits while still maintaining complete testability. In each case, the emphasis is on obtaining circuits which are fully path-delay-fault testable. In the process of design modification to produce fully robustly testable structures, we have derived a number of new composition rules that allow cascading individual modules while maintaining robust testability under dynamic fault models. United States. Defense Advanced Research Projects Agency (Contract N00014-87-K-0825) National Science Foundation (U.S.) (Young Investigator Award) 2015-03-20T18:11:20Z 2015-03-20T18:11:20Z 1993 2015-03-19T11:37:48Z Article http://purl.org/eprint/type/JournalArticle 1065-514X 1563-5171 http://hdl.handle.net/1721.1/96136 Bryan, Michael J., Srinivas Devadas, and Kurt Keutzer. “Analysis and Design of Regular Structures for Robust Dynamic Fault Testability.” VLSI Design 1, no. 1 (1993): 45–60. © 1993 Hindawi Publishing Corporation https://orcid.org/0000-0001-8253-7714 en http://dx.doi.org/10.1155/1993/38536 VLSI Design Creative Commons Attribution http://creativecommons.org/licenses/by/2.0 Copyright © 1993 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. application/pdf Hindawi Publishing Corporation Hindawi Publishing Corporation |
| spellingShingle | Bryan, Michael J. Devadas, Srinivas Keutzer, Kurt Analysis and Design of Regular Structures for Robust Dynamic Fault Testability |
| title | Analysis and Design of Regular Structures for Robust Dynamic Fault Testability |
| title_full | Analysis and Design of Regular Structures for Robust Dynamic Fault Testability |
| title_fullStr | Analysis and Design of Regular Structures for Robust Dynamic Fault Testability |
| title_full_unstemmed | Analysis and Design of Regular Structures for Robust Dynamic Fault Testability |
| title_short | Analysis and Design of Regular Structures for Robust Dynamic Fault Testability |
| title_sort | analysis and design of regular structures for robust dynamic fault testability |
| url | http://hdl.handle.net/1721.1/96136 https://orcid.org/0000-0001-8253-7714 |
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