Analysis and Design of Regular Structures for Robust Dynamic Fault Testability
Recent methods of synthesizing logic that is fully and robustly testable for dynamic faults, namely path delay, transistor stuck-open and gate delay faults, rely almost exclusively on flattening given logic expressions into sum-of-products form, minimizing the cover to obtain a fully dynamic-fault t...
| Main Authors: | , , |
|---|---|
| Other Authors: | |
| Format: | Article |
| Language: | English |
| Published: |
Hindawi Publishing Corporation
2015
|
| Online Access: | http://hdl.handle.net/1721.1/96136 https://orcid.org/0000-0001-8253-7714 |