A Low-Latency, Low-Area Hardware Oblivious RAM Controller
We build and evaluate Tiny ORAM, an Oblivious RAM prototype on FPGA. Oblivious RAM is a cryptographic primitive that completely obfuscates an application’s data, access pattern, and read/write behavior to/from external memory (such as DRAM or disk). Tiny ORAM makes two main contributions. First, by...
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| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers (IEEE)
2015
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| Online Access: | http://hdl.handle.net/1721.1/96843 https://orcid.org/0000-0001-8253-7714 https://orcid.org/0000-0003-3437-7570 https://orcid.org/0000-0002-7044-5684 https://orcid.org/0000-0003-1467-2150 |
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| author | Fletcher, Christopher Wardlaw Ren, Ling Kwon, Young Hyun van Dijk, Marten Stefanov, Emil Serpanos, Dimitrios Devadas, Srinivas |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Fletcher, Christopher Wardlaw Ren, Ling Kwon, Young Hyun van Dijk, Marten Stefanov, Emil Serpanos, Dimitrios Devadas, Srinivas |
| author_sort | Fletcher, Christopher Wardlaw |
| collection | MIT |
| description | We build and evaluate Tiny ORAM, an Oblivious RAM prototype on FPGA. Oblivious RAM is a cryptographic primitive that completely obfuscates an application’s data, access pattern, and read/write behavior to/from external memory (such as DRAM or disk). Tiny ORAM makes two main contributions. First, by removing an algorithmic bottleneck in prior work, Tiny ORAM is the first hardware ORAM design to support arbitrary block sizes (e.g., 64 Bytes to 4096 Bytes). With a 64 Byte block size, Tiny ORAM can finish an access in 1.4 µs, over 40X faster than the prior-art implementation. Second, through novel algorithmic and engineering-level optimizations, Tiny ORAM reduces the number of symmetric encryption operations by ~ 3X compared to a prior work. Tiny ORAM is also the first design to implement and report real numbers for the cost of symmetric encryption in hardware ORAM constructions. Putting it together, Tiny ORAM requires 18381 (5%) LUTs and 146 (13%) Block RAM on a Xilinx XC7VX485T FPGA, including the cost of encryption |
| first_indexed | 2024-09-23T17:08:46Z |
| format | Article |
| id | mit-1721.1/96843 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T17:08:46Z |
| publishDate | 2015 |
| publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| record_format | dspace |
| spelling | mit-1721.1/968432022-09-29T23:56:29Z A Low-Latency, Low-Area Hardware Oblivious RAM Controller Fletcher, Christopher Wardlaw Ren, Ling Kwon, Young Hyun van Dijk, Marten Stefanov, Emil Serpanos, Dimitrios Devadas, Srinivas Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Fletcher, Christopher Wardlaw Ren, Ling Kwon, Young Hyun Devadas, Srinivas We build and evaluate Tiny ORAM, an Oblivious RAM prototype on FPGA. Oblivious RAM is a cryptographic primitive that completely obfuscates an application’s data, access pattern, and read/write behavior to/from external memory (such as DRAM or disk). Tiny ORAM makes two main contributions. First, by removing an algorithmic bottleneck in prior work, Tiny ORAM is the first hardware ORAM design to support arbitrary block sizes (e.g., 64 Bytes to 4096 Bytes). With a 64 Byte block size, Tiny ORAM can finish an access in 1.4 µs, over 40X faster than the prior-art implementation. Second, through novel algorithmic and engineering-level optimizations, Tiny ORAM reduces the number of symmetric encryption operations by ~ 3X compared to a prior work. Tiny ORAM is also the first design to implement and report real numbers for the cost of symmetric encryption in hardware ORAM constructions. Putting it together, Tiny ORAM requires 18381 (5%) LUTs and 146 (13%) Block RAM on a Xilinx XC7VX485T FPGA, including the cost of encryption Qatar Computing Research Institute (QCRI-CSAIL Parternship) National Science Foundation (U.S.) American Society for Engineering Education. National Defense Science and Engineering Graduate Fellowship 2015-04-29T14:55:18Z 2015-04-29T14:55:18Z 2015-05 Article http://purl.org/eprint/type/ConferencePaper http://hdl.handle.net/1721.1/96843 Fletcher, Christopher W., Ling Ren, Albert Kwon, Marten van Dijk, Emil Stefanov, Dimitrios Serpanos, and Srinivas Devadas. "A Low-Latency, Low-Area Hardware Oblivious RAM Controller." IEEE 23rd International Symposium on Field-Programmable Custom Computing Machines, May 3-5, 2015. https://orcid.org/0000-0001-8253-7714 https://orcid.org/0000-0003-3437-7570 https://orcid.org/0000-0002-7044-5684 https://orcid.org/0000-0003-1467-2150 en_US http://fccm.org/2015/programme.html#programme Proceedings of the IEEE 23rd International Symposium on Field-Programmable Custom Computing Machines Creative Commons Attribution-Noncommercial-Share Alike http://creativecommons.org/licenses/by-nc-sa/4.0/ application/pdf Institute of Electrical and Electronics Engineers (IEEE) Fletcher |
| spellingShingle | Fletcher, Christopher Wardlaw Ren, Ling Kwon, Young Hyun van Dijk, Marten Stefanov, Emil Serpanos, Dimitrios Devadas, Srinivas A Low-Latency, Low-Area Hardware Oblivious RAM Controller |
| title | A Low-Latency, Low-Area Hardware Oblivious RAM Controller |
| title_full | A Low-Latency, Low-Area Hardware Oblivious RAM Controller |
| title_fullStr | A Low-Latency, Low-Area Hardware Oblivious RAM Controller |
| title_full_unstemmed | A Low-Latency, Low-Area Hardware Oblivious RAM Controller |
| title_short | A Low-Latency, Low-Area Hardware Oblivious RAM Controller |
| title_sort | low latency low area hardware oblivious ram controller |
| url | http://hdl.handle.net/1721.1/96843 https://orcid.org/0000-0001-8253-7714 https://orcid.org/0000-0003-3437-7570 https://orcid.org/0000-0002-7044-5684 https://orcid.org/0000-0003-1467-2150 |
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